summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2020-10-22 14:13:14 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-11-05 00:02:07 +0000
commit1410224cf476ed5e666deffcbbc455055632add1 (patch)
tree23f3df4f4588eb9de5efd8fb74289e1e62667724 /src/mainboard
parent6c49f40b6e6342b7acb47cb0a57fa10269e3d4c9 (diff)
soc/intel/xeon_sp: Use common cpu/intel romstage entry
This removes some boilerplate like starting the console and also adds a "start of romstage" timestamp. Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard')
0 files changed, 0 insertions, 0 deletions