diff options
| author | Abhay Kumar <abhay.kumar@intel.com> | 2016-05-18 18:29:12 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-26 17:26:23 +0200 |
| commit | 1285598a994483e032d9495060b8f638d671cbe5 (patch) | |
| tree | 6132f21778a29bba5c65e46725db4505005ede2e /src/mainboard | |
| parent | 988b3fd2ee3f761340d43a09af12d2b66f841b5a (diff) | |
mainboard/intel/amenia: Configure DDI0, DDI1 HPD GPIO lines.
1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.
2. Make 20k Pullup and remove duplicate code.
Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14899
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/intel/amenia/mainboard.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index e0c3fc9c9a..22304f8140 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -114,9 +114,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ - PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */ - PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */ - PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */ PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */ @@ -129,9 +126,9 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */ - PAD_CFG_NF(GPIO_199,NATIVE,DEEP,NF2), /* HV_DDI1_HPD */ - PAD_CFG_NF(GPIO_200,NATIVE,DEEP,NF2), /* HV_DDI0_HPD */ - PAD_CFG_NF(PMC_SPI_FS1,NATIVE,DEEP,NF2), /* HV_DDI2_HPD */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ + PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ }; |