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authorShelley Chen <shchen@chromium.org>2018-03-16 12:43:02 -0700
committerMartin Roth <martinroth@google.com>2018-03-19 14:23:03 +0000
commitf12bb7bcf2894eb226028bf960621ccfc680ac71 (patch)
treeb6eaebae67b46684846bdd246213990382895f66 /src/mainboard
parent6dfbb593077ea3edb9162431c2380a268d35fc4a (diff)
mb/google/fizz: Enable VMX
We are enabling at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot, clearing the ramoops logs. Enabling in BIOS so it matches what the kernel expects. This is the same change that were done for eve: https://review.coreboot.org/#/c/22449/ BUG=None BRANCH=None TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT check for /dev/pstore/console-ramoops Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/fizz/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index e7654cfa98..d5ee04f716 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -89,6 +89,7 @@ chip soc/intel/skylake
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "SendVrMbxCmd" = "1" # IMVP8 workaround
+ register "VmxEnable" = "1"
# Intersil VR c-state issue workaround
# send VR mailbox command for IA/GT/SA rails