tegra124/nyan: display, clock, and other updates

tegra124: Set Tx FIFO threshold value to recommended setting
Reviewed-on: https://chromium-review.googlesource.com/175200
(cherry picked from commit c8f086711c6ae2db70fc8e0d84b54f5952fbe0ad)

tegra124: add CLK_X definitions
Reviewed-on: https://chromium-review.googlesource.com/175220
(cherry picked from commit 3f8a844bd2f151e06d82d1a7fac4492c6bc9417d)

tegra124: fix incorrect struct member in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/175270
(cherry picked from commit 967193d5984a086c297988caa580b61cb4d0414c)

tegra124: add the _x clocks to clock_enable_clear_reset
Reviewed-on: https://chromium-review.googlesource.com/175539
(cherry picked from commit df4c515d73b02061e5c98f51efd50e04b10d63f5)

tegra124: add clock support code for graphics.
Reviewed-on: https://chromium-review.googlesource.com/175162
(cherry picked from commit b8eb6ab4cdc5a583636c10fa05f947a244f94819)

tegra124: Clean up some #defines for DMA
Reviewed-on: https://chromium-review.googlesource.com/175631
(cherry picked from commit 1a0a900f2d060916c9878781b82113b16a7945d9)

tegra124: enable flow control for APBDMA in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/175630
(cherry picked from commit 873e6f9e95f6cb0162fa06216682fbc71ab0202d)

nyan: move clock setup for the display out of dca_init
Reviewed-on: https://chromium-review.googlesource.com/175656
(cherry picked from commit 32dd9947a60298ff9488c911629802c257ed6afc)

tegra124: more display PLL setup and clock hardcode removal.
Reviewed-on: https://chromium-review.googlesource.com/175732
(cherry picked from commit 80402876b5daa9e9389fd4fab5f539d89c37fa7f)

tegra124: move dp.c from tegra to tegra124
Reviewed-on: https://chromium-review.googlesource.com/175830
(cherry picked from commit e98be569b0ba7f4d565ce677343a317db08344e0)

tegra124: clean up tabbing; nyan: add a comment and setting to devicetree.cb
Reviewed-on: https://chromium-review.googlesource.com/175889
(cherry picked from commit 4e513196b0014c5a82079f3aa87c2efbeb645484)

tegra: get rid of struct members that are not used
Reviewed-on: https://chromium-review.googlesource.com/176023
(cherry picked from commit 032b8a0c9fe0152ebc27344e93128865ecb918a6)

tegra124: Increase SCLK (AVP) to 300MHz
Reviewed-on: https://chromium-review.googlesource.com/175489
(cherry picked from commit 7e082f2c2f030950d652f1f87f637e15dee38552)

tegra124: Address old main CPU starting review feedback.
Reviewed-on: https://chromium-review.googlesource.com/175933
(cherry picked from commit 1d76ac71bd839dff9198e65132ec25212dd55ffd)

tegra124: Revise clock source configuration for irregular peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176109
(cherry picked from commit 1021c215190602a2b8c1ab97d6c8313d89597d99)

nyan: add timestamps in romstage
Reviewed-on: https://chromium-review.googlesource.com/176172
(cherry picked from commit cd626aa10b56cd4da6ebda36fe487e44b08f3935)

tegra124: Allow enabling clock output for external peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176108
(cherry picked from commit ea9fb6393ee80da77c9fbc30f605859c7009c9ed)

nyan: Enable and configure clocks for I2S and audio codec.
Reviewed-on: https://chromium-review.googlesource.com/176104
(cherry picked from commit 1fb659b3e73285ff8218c0f229734edd3b979ca4)

tegra124: Fix typo in pinmux name.
Reviewed-on: https://chromium-review.googlesource.com/176215
(cherry picked from commit c7915ad41a3f1d1452aa6d6d287aaa8eb9e85c34)

nyan: Add pinmux settings for audio peripherals.
Reviewed-on: https://chromium-review.googlesource.com/176212
(cherry picked from commit 37412f3201590e47a06d4678fa833164d370b41c)

nyan: De-array-ify the PMIC setup code.
Reviewed-on: https://chromium-review.googlesource.com/176903
(cherry picked from commit 86ab1ce9fbf6d5362af1ee37de1394412366f247)

nyan: Add a kconfig for building for the original nyans in pixel cases.
Reviewed-on: https://chromium-review.googlesource.com/176904
(cherry picked from commit 1d05fd5bc40d727826510ec81496ce4a49e257ed)

nyan: Set the CPU voltage differently depending on which PMIC is in use.
Reviewed-on: https://chromium-review.googlesource.com/176905
(cherry picked from commit 31507f6a575220737ee5683b312cd162600f89cc)

nyan: Increase the CPU voltage to 1.2V.
Reviewed-on: https://chromium-review.googlesource.com/176906
(cherry picked from commit fe4795e66b515c2523df09a8800ecac9a3f63557)

tegra124: Flesh out/tidy up the flow controller constants.
Reviewed-on: https://chromium-review.googlesource.com/177085
(cherry picked from commit b50d315506a5ab9c81b6bbaf8cf580dbb3e78794)

tegra124: When leaving the bootblock/AVP, really stop the AVP.
Reviewed-on: https://chromium-review.googlesource.com/177086
(cherry picked from commit 06c10df889d4d935bc99792df860d93766ae44dd)

nyan: Set SPI4 speed to 33MHz
Reviewed-on: https://chromium-review.googlesource.com/177038
(cherry picked from commit c98de65482fabdb5c76944fe3bf762191b3a0a55)

nyan: Do console_init() in romstage
Reviewed-on: https://chromium-review.googlesource.com/176763
(cherry picked from commit 0bec32e09eab28bc5ea49b7896a8b6f489143b03)

nyan: Add a prompt to the CONFIG_NYAN_IN_A_PIXEL option.
Reviewed-on: https://chromium-review.googlesource.com/177486
(cherry picked from commit 7cbb801d000dac4b39f76266ebef2585fe48faba)

nyan: Separate the SDRAM BCT config for the two nyans, and turn down norrin.
Reviewed-on: https://chromium-review.googlesource.com/177487
(cherry picked from commit 6b119685f6626d79d924af9f856ebb90af45a73f)

tegra124: Bump up HCLK and PCLK
Reviewed-on: https://chromium-review.googlesource.com/177563
(cherry picked from commit c25337dac8c3ecdd8ffe5b4d11acebb216132405)

nyan: Add some code for reading the board ID.
Reviewed-on: https://chromium-review.googlesource.com/177488
(cherry picked from commit 5fccbce99e7db312e2e3caf806c438c9b04c0a8f)

nyan: Use the board ID to decide how to initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/177489
(cherry picked from commit 677bdb9df55248da3a0c6be0089098f6d6807d3c)

nyan: Create kconfig variables for each SDRAM config.
Reviewed-on: https://chromium-review.googlesource.com/177580
(cherry picked from commit d7ddcf262a321f06289c4f2b2a6b43982dd96377)

tegra124: Mux some unused pins away from UARTA, and pull up the serial RX line.
Reviewed-on: https://chromium-review.googlesource.com/177637
(cherry picked from commit bd533cc109b0acf3495b04fa6622e250ba454fe9)

tegra124: Initialize the MCR when setting up the UART.
Reviewed-on: https://chromium-review.googlesource.com/177638
(cherry picked from commit 38c84786fc3e8fab913aebca176ac7b038cb0be6)

tegra124: fix SPI AHB burst length
Reviewed-on: https://chromium-review.googlesource.com/177564
(cherry picked from commit f29235263202c9b4a3dbb65da5727c8eefe44315)

tegra124: remove unneeded debug print in SPI code
Reviewed-on: https://chromium-review.googlesource.com/177833
(cherry picked from commit 34a50040268dbde1c326d315f8042a3905ddfb06)

nyan: Set up the SOC and TPM reset pin.
Reviewed-on: https://chromium-review.googlesource.com/177965
(cherry picked from commit b81a5bd15a2979ee009b9f7bc4a39a304e6a759a)

tegra124: Allow some time for packets to appear in Rx FIFO
Reviewed-on: https://chromium-review.googlesource.com/177832
(cherry picked from commit 8f70a25b1eea865a448525749ac18393f5b9ad84)

nyan: PMIC: Slam default init values for SDOs/LDOs in AS3722
Reviewed-on: https://chromium-review.googlesource.com/178226
(cherry picked from commit c536b0d82fd6fffbc0e2448e0d19d3f06df5d86a)

nyan: change devicetree for the new display settings.
Reviewed-on: https://chromium-review.googlesource.com/177958
(cherry picked from commit 43abed730f222c8a685c250a58c981268994a65d)

nyan: Switch USB VBUS GPIOs from outputs to pulled-up inputs
Reviewed-on: https://chromium-review.googlesource.com/178914
(cherry picked from commit e47b6a609b9d23694a466b56960d9d14ca5d6242)

Tegra124: nyan: Disable VPR
Reviewed-on: https://chromium-review.googlesource.com/179327
(cherry picked from commit 441aa276446141f1b92ed8fb98c9578597487f4d)

tegra124: norrin: fix display issue
Reviewed-on: https://chromium-review.googlesource.com/179745
(cherry picked from commit c1c1ae69f6058ed901f532e2c532d1e6ba1f81fb)

tegra124: Add iRAM layout information.
Reviewed-on: https://chromium-review.googlesource.com/179814
(cherry picked from commit d00f135c93a52ad4dced2edecb74e2dfc54bb2fa)

tegra124: Run bootblock and ROM stage out of DRAM.
Reviewed-on: https://chromium-review.googlesource.com/179822
(cherry picked from commit 2d3ec06ec39a489d02e798bb22bce4d7465b20ce)

nyan: clean up a comment regarding video
Reviewed-on: https://chromium-review.googlesource.com/180161
(cherry picked from commit 03b5e88a66b9c96df2ef3d9ce5ba4a62a8bb2447)

tegra124: norrin: the first step to clean up display code
Reviewed-on: https://chromium-review.googlesource.com/180135
(cherry picked from commit 9d0c12dfef28a1161604df9b3fcc113049b2747d)

Squashed 49 commits for tegra124/nyan.

Change-Id: Id67bfee725e703d3e2d8ac17f40844dc193e901d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

13 files changed, 640 insertions, 66 deletions

diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
index 4a14b157c3..1a7b2604b0 100644
--- a/src/mainboard/google/nyan/Kconfig
+++ b/src/mainboard/google/nyan/Kconfig
@@ -87,4 +87,18 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex
 	default 1
 
+choice
+	prompt "BCT sdram configuration"
+	default BCT_SDRAM_792
+	help
+	  The SDRAM configuration to put in the BCT.
+
+config BCT_SDRAM_792
+	bool "792 MHz"
+
+config BCT_SDRAM_924
+	bool "924 MHz"
+
+endchoice
+
 endif # BOARD_GOOGLE_NYAN
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
index 49ccf39ac7..e612af3551 100644
--- a/src/mainboard/google/nyan/Makefile.inc
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -27,6 +27,7 @@ $(obj)/generated/bct.cfg:
 
 subdirs-y += bct
 
+bootblock-y += boardid.c
 bootblock-y += bootblock.c
 bootblock-y += pmic.c
 
diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc
index 2442c53e8c..52251c4f2b 100644
--- a/src/mainboard/google/nyan/bct/Makefile.inc
+++ b/src/mainboard/google/nyan/bct/Makefile.inc
@@ -20,4 +20,5 @@
 bct-cfg-$(CONFIG_BCT_CFG_EMMC) += emmc.cfg
 bct-cfg-$(CONFIG_BCT_CFG_SPI) += spi.cfg
 bct-cfg-y += odmdata.cfg
-bct-cfg-y += sdram.cfg
+bct-cfg-$(CONFIG_BCT_SDRAM_924) += sdram-924.cfg
+bct-cfg-$(CONFIG_BCT_SDRAM_792) += sdram-792.cfg
diff --git a/src/mainboard/google/nyan/bct/sdram-792.cfg b/src/mainboard/google/nyan/bct/sdram-792.cfg
new file mode 100644
index 0000000000..d4d96600a5
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/sdram-792.cfg
@@ -0,0 +1,346 @@
+# CFG Version 07
+# Do not edit. Generated by gen_sdram_cfg V4.0.7. Command:
+#   gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.262 -dram_board_cfg 10 -fly_by_time_ps 1650
+#      -b PM358/PM358_792MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_792Mhz.cfg
+# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.26 ns (792.39 MHz)
+# bkv file: PM358/PM358_792MHz_emc_reg.txt
+SDRAM[0].MemoryType                               = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMInputDivider                         = 0x00000001;
+SDRAM[0].PllMFeedbackDivider                      = 0x00000042;
+SDRAM[0].PllMStableTime                           = 0x0000012c;
+SDRAM[0].PllMSetupControl                         = 0x00000000;
+SDRAM[0].PllMSelectDiv2                           = 0x00000000;
+SDRAM[0].PllMPDLshiftPh45                         = 0x00000001;
+SDRAM[0].PllMPDLshiftPh90                         = 0x00000001;
+SDRAM[0].PllMPDLshiftPh135                        = 0x00000001;
+SDRAM[0].PllMKCP                                  = 0x00000000;
+SDRAM[0].PllMKVCO                                 = 0x00000000;
+SDRAM[0].EmcBctSpare0                             = 0x00000000;
+SDRAM[0].EmcBctSpare1                             = 0x00000000;
+SDRAM[0].EmcBctSpare2                             = 0x00000000;
+SDRAM[0].EmcBctSpare3                             = 0x00000000;
+SDRAM[0].EmcBctSpare4                             = 0x00000000;
+SDRAM[0].EmcBctSpare5                             = 0x00000000;
+SDRAM[0].EmcBctSpare6                             = 0x00000000;
+SDRAM[0].EmcBctSpare7                             = 0x00000000;
+SDRAM[0].EmcBctSpare8                             = 0x00000000;
+SDRAM[0].EmcBctSpare9                             = 0x00000000;
+SDRAM[0].EmcBctSpare10                            = 0x00000000;
+SDRAM[0].EmcBctSpare11                            = 0x00000000;
+SDRAM[0].EmcClockSource                           = 0x80000000;
+SDRAM[0].EmcAutoCalInterval                       = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig                         = 0xa1430000;
+SDRAM[0].EmcAutoCalConfig2                        = 0x00000000;
+SDRAM[0].EmcAutoCalConfig3                        = 0x00000000;
+SDRAM[0].EmcAutoCalWait                           = 0x00000190;
+SDRAM[0].EmcAdrCfg                                = 0x00000000;
+SDRAM[0].EmcPinProgramWait                        = 0x00000001;
+SDRAM[0].EmcPinExtraWait                          = 0x00000000;
+SDRAM[0].EmcTimingControlWait                     = 0x00000000;
+SDRAM[0].EmcRc                                    = 0x00000025;
+SDRAM[0].EmcRfc                                   = 0x000000cd;
+SDRAM[0].EmcRfcSlr                                = 0x00000000;
+SDRAM[0].EmcRas                                   = 0x00000019;
+SDRAM[0].EmcRp                                    = 0x0000000a;
+SDRAM[0].EmcR2r                                   = 0x00000000;
+SDRAM[0].EmcW2w                                   = 0x00000000;
+SDRAM[0].EmcR2w                                   = 0x00000007;
+SDRAM[0].EmcW2r                                   = 0x0000000d;
+SDRAM[0].EmcR2p                                   = 0x00000004;
+SDRAM[0].EmcW2p                                   = 0x00000013;
+SDRAM[0].EmcRdRcd                                 = 0x0000000a;
+SDRAM[0].EmcWrRcd                                 = 0x0000000a;
+SDRAM[0].EmcRrd                                   = 0x00000003;
+SDRAM[0].EmcRext                                  = 0x00000002;
+SDRAM[0].EmcWext                                  = 0x00000000;
+SDRAM[0].EmcWdv                                   = 0x00000006;
+SDRAM[0].EmcWdvMask                               = 0x00000006;
+SDRAM[0].EmcQUse                                  = 0x0000000b;
+SDRAM[0].EmcQuseWidth                             = 0x00000002;
+SDRAM[0].EmcIbdly                                 = 0x00000000;
+SDRAM[0].EmcEInput                                = 0x00000003;
+SDRAM[0].EmcEInputDuration                        = 0x0000000c;
+SDRAM[0].EmcPutermExtra                           = 0x00090000;
+SDRAM[0].EmcPutermWidth                           = 0x00000004;
+SDRAM[0].EmcPutermAdj                             = 0x00000000;
+SDRAM[0].EmcCdbCntl1                              = 0x00000000;
+SDRAM[0].EmcCdbCntl2                              = 0x00000000;
+SDRAM[0].EmcCdbCntl3                              = 0x00000000;
+SDRAM[0].EmcQRst                                  = 0x00000002;
+SDRAM[0].EmcQSafe                                 = 0x00000011;
+SDRAM[0].EmcRdv                                   = 0x00000017;
+SDRAM[0].EmcRdvMask                               = 0x00000019;
+SDRAM[0].EmcQpop                                  = 0x0000000f;
+SDRAM[0].EmcCtt                                   = 0x00000000;
+SDRAM[0].EmcCttDuration                           = 0x00000004;
+SDRAM[0].EmcRefresh                               = 0x000017eb;
+SDRAM[0].EmcBurstRefreshNum                       = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt                      = 0x000005fa;
+SDRAM[0].EmcPdEx2Wr                               = 0x00000003;
+SDRAM[0].EmcPdEx2Rd                               = 0x00000003;
+SDRAM[0].EmcPChg2Pden                             = 0x00000001;
+SDRAM[0].EmcAct2Pden                              = 0x00000000;
+SDRAM[0].EmcAr2Pden                               = 0x000000c7;
+SDRAM[0].EmcRw2Pden                               = 0x00000018;
+SDRAM[0].EmcTxsr                                  = 0x000000d7;
+SDRAM[0].EmcTxsrDll                               = 0x00000200;
+SDRAM[0].EmcTcke                                  = 0x00000005;
+SDRAM[0].EmcTckesr                                = 0x00000006;
+SDRAM[0].EmcTpd                                   = 0x00000005;
+SDRAM[0].EmcTfaw                                  = 0x0000001d;
+SDRAM[0].EmcTrpab                                 = 0x00000000;
+SDRAM[0].EmcTClkStable                            = 0x00000008;
+SDRAM[0].EmcTClkStop                              = 0x00000008;
+SDRAM[0].EmcTRefBw                                = 0x0000182c;
+SDRAM[0].EmcFbioCfg5                              = 0x104ab898;
+SDRAM[0].EmcFbioCfg6                              = 0x00000002;
+SDRAM[0].EmcFbioSpare                             = 0x00000000;
+SDRAM[0].EmcCfgRsv                                = 0xff00ff00;
+SDRAM[0].EmcMrs                                   = 0x80001d71;
+SDRAM[0].EmcEmrs                                  = 0x80100002;
+SDRAM[0].EmcEmrs2                                 = 0x80200018;
+SDRAM[0].EmcEmrs3                                 = 0x80300000;
+SDRAM[0].EmcMrw1                                  = 0x00000000;
+SDRAM[0].EmcMrw2                                  = 0x00000000;
+SDRAM[0].EmcMrw3                                  = 0x00000000;
+SDRAM[0].EmcMrw4                                  = 0x00000000;
+SDRAM[0].EmcMrwExtra                              = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra                      = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable       = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable               = 0x00000000;
+SDRAM[0].EmcMrwResetCommand                       = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait                     = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt                            = 0x00f7000e;
+SDRAM[0].EmcMrsWaitCnt2                           = 0x00f7000e;
+SDRAM[0].EmcCfg                                   = 0x73300000;
+SDRAM[0].EmcCfg2                                  = 0x0000089d;
+SDRAM[0].EmcCfgPipe                               = 0x000040a0;
+SDRAM[0].EmcDbg                                   = 0x01000c00;
+SDRAM[0].EmcCmdQ                                  = 0x10004408;
+SDRAM[0].EmcMc2EmcQ                               = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl                     = 0x80003025;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone        = 0x00000001;
+SDRAM[0].EmcCfgDigDll                             = 0xe00701b1;
+SDRAM[0].EmcCfgDigDllPeriod                       = 0x00008000;
+SDRAM[0].EmcDevSelect                             = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl                            = 0x00040000;
+SDRAM[0].EmcDllXformDqs0                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs1                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs2                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs3                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs4                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs5                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs6                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs7                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs8                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs9                          = 0x00000008;
+SDRAM[0].EmcDllXformDqs10                         = 0x00000008;
+SDRAM[0].EmcDllXformDqs11                         = 0x00000008;
+SDRAM[0].EmcDllXformDqs12                         = 0x00000008;
+SDRAM[0].EmcDllXformDqs13                         = 0x00000008;
+SDRAM[0].EmcDllXformDqs14                         = 0x00000008;
+SDRAM[0].EmcDllXformDqs15                         = 0x00000008;
+SDRAM[0].EmcDllXformQUse0                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse1                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse2                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse3                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse4                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse5                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse6                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse7                         = 0x00000000;
+SDRAM[0].EmcDllXformAddr0                         = 0x0000000e;
+SDRAM[0].EmcDllXformAddr1                         = 0x0000000e;
+SDRAM[0].EmcDllXformAddr2                         = 0x00000000;
+SDRAM[0].EmcDllXformAddr3                         = 0x0000000e;
+SDRAM[0].EmcDllXformAddr4                         = 0x00000000;
+SDRAM[0].EmcDllXformAddr5                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse8                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse9                         = 0x00000000;
+SDRAM[0].EmcDllXformQUse10                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse11                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse12                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse13                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse14                        = 0x00000000;
+SDRAM[0].EmcDllXformQUse15                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs8                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs9                         = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs10                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs11                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs12                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs13                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs14                        = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs15                        = 0x00000000;
+SDRAM[0].EmcDllXformDq0                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq1                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq2                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq3                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq4                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq5                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq6                           = 0x0000000b;
+SDRAM[0].EmcDllXformDq7                           = 0x0000000b;
+SDRAM[0].WarmBootWait                             = 0x00000002;
+SDRAM[0].EmcCttTermCtrl                           = 0x00000802;
+SDRAM[0].EmcOdtWrite                              = 0x00000000;
+SDRAM[0].EmcOdtRead                               = 0x00000000;
+SDRAM[0].EmcZcalInterval                          = 0x00020000;
+SDRAM[0].EmcZcalWaitCnt                           = 0x00000042;
+SDRAM[0].EmcZcalMrwCmd                            = 0x80000000;
+SDRAM[0].EmcMrsResetDll                           = 0x00000000;
+SDRAM[0].EmcZcalInitDev0                          = 0x80000011;
+SDRAM[0].EmcZcalInitDev1                          = 0x00000000;
+SDRAM[0].EmcZcalInitWait                          = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables               = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot                 = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot                     = 0x00000000;
+SDRAM[0].EmcZcalWarmBootWait                      = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable                     = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait                       = 0x00000000;
+SDRAM[0].EmcMrsExtra                              = 0x80001d71;
+SDRAM[0].EmcWarmBootMrsExtra                      = 0x80100002;
+SDRAM[0].EmcEmrsDdr2DllEnable                     = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset                       = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib                      = 0x00000000;
+SDRAM[0].EmcDdr2Wait                              = 0x00000000;
+SDRAM[0].EmcClkenOverride                         = 0x00000000;
+SDRAM[0].McDisExtraSnapLevels                     = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum                       = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot              = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot               = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot               = 0x00000003;
+SDRAM[0].PmcVddpSel                               = 0x00000002;
+SDRAM[0].PmcVddpSelWait                           = 0x00000002;
+SDRAM[0].PmcDdrPwr                                = 0x00000003;
+SDRAM[0].PmcDdrCfg                                = 0x00002002;
+SDRAM[0].PmcIoDpd3Req                             = 0x4fff2f97;
+SDRAM[0].PmcIoDpd3ReqWait                         = 0x00000000;
+SDRAM[0].PmcRegShort                              = 0x00000000;
+SDRAM[0].PmcNoIoPower                             = 0x00000000;
+SDRAM[0].PmcPorDpdCtrlWait                        = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl                         = 0x100002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2                        = 0x770c0000;
+SDRAM[0].EmcXm2CmdPadCtrl3                        = 0x050c0000;
+SDRAM[0].EmcXm2CmdPadCtrl4                        = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl5                        = 0x00111111;
+SDRAM[0].EmcXm2DqsPadCtrl                         = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2                        = 0x0020013d;
+SDRAM[0].EmcXm2DqsPadCtrl3                        = 0x61861820;
+SDRAM[0].EmcXm2DqsPadCtrl4                        = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl5                        = 0x00514514;
+SDRAM[0].EmcXm2DqsPadCtrl6                        = 0x61861800;
+SDRAM[0].EmcXm2DqPadCtrl                          = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2                         = 0x00000000;
+SDRAM[0].EmcXm2DqPadCtrl3                         = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl                         = 0x77ffc085;
+SDRAM[0].EmcXm2ClkPadCtrl2                        = 0x00000707;
+SDRAM[0].EmcXm2CompPadCtrl                        = 0x81f1f108;
+SDRAM[0].EmcXm2VttGenPadCtrl                      = 0x07070004;
+SDRAM[0].EmcXm2VttGenPadCtrl2                     = 0x00000000;
+SDRAM[0].EmcXm2VttGenPadCtrl3                     = 0x017fffff;
+SDRAM[0].EmcAcpdControl                           = 0x00000000;
+SDRAM[0].EmcSwizzleRank0ByteCfg                   = 0x00003120;
+SDRAM[0].EmcSwizzleRank0Byte0                     = 0x25143067;
+SDRAM[0].EmcSwizzleRank0Byte1                     = 0x45367102;
+SDRAM[0].EmcSwizzleRank0Byte2                     = 0x47106253;
+SDRAM[0].EmcSwizzleRank0Byte3                     = 0x04362175;
+SDRAM[0].EmcSwizzleRank1ByteCfg                   = 0x00003120;
+SDRAM[0].EmcSwizzleRank1Byte0                     = 0x71546032;
+SDRAM[0].EmcSwizzleRank1Byte1                     = 0x35104276;
+SDRAM[0].EmcSwizzleRank1Byte2                     = 0x27043615;
+SDRAM[0].EmcSwizzleRank1Byte3                     = 0x72306145;
+SDRAM[0].EmcDsrVttgenDrv                          = 0x0505003f;
+SDRAM[0].EmcTxdsrvttgen                           = 0x00000000;
+SDRAM[0].EmcBgbiasCtl0                            = 0x00000000;
+SDRAM[0].McEmemAdrCfg                             = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0                         = 0x00080303;
+SDRAM[0].McEmemAdrCfgDev1                         = 0x00080303;
+SDRAM[0].McEmemAdrCfgBankMask0                    = 0x00001248;
+SDRAM[0].McEmemAdrCfgBankMask1                    = 0x00002490;
+SDRAM[0].McEmemAdrCfgBankMask2                    = 0x00000920;
+SDRAM[0].McEmemAdrCfgBankSwizzle3                 = 0x00000001;
+SDRAM[0].McEmemCfg                                = 0x00000800;
+SDRAM[0].McEmemArbCfg                             = 0x0e00000b;
+SDRAM[0].McEmemArbOutstandingReq                  = 0x80000040;
+SDRAM[0].McEmemArbTimingRcd                       = 0x00000004;
+SDRAM[0].McEmemArbTimingRp                        = 0x00000005;
+SDRAM[0].McEmemArbTimingRc                        = 0x00000013;
+SDRAM[0].McEmemArbTimingRas                       = 0x0000000c;
+SDRAM[0].McEmemArbTimingFaw                       = 0x0000000f;
+SDRAM[0].McEmemArbTimingRrd                       = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre                   = 0x00000003;
+SDRAM[0].McEmemArbTimingWap2Pre                   = 0x0000000c;
+SDRAM[0].McEmemArbTimingR2R                       = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W                       = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W                       = 0x00000005;
+SDRAM[0].McEmemArbTimingW2R                       = 0x00000008;
+SDRAM[0].McEmemArbDaTurns                         = 0x08050202;
+SDRAM[0].McEmemArbDaCovers                        = 0x00170e13;
+SDRAM[0].McEmemArbMisc0                           = 0x736c2414;
+SDRAM[0].McEmemArbMisc1                           = 0x70000f02;
+SDRAM[0].McEmemArbRing1Throttle                   = 0x001f0000;
+SDRAM[0].McEmemArbOverride                        = 0x10000000;
+SDRAM[0].McEmemArbOverride1                       = 0x00000000;
+SDRAM[0].McEmemArbRsv                             = 0xff00ff00;
+SDRAM[0].McClkenOverride                          = 0x00000000;
+SDRAM[0].McStatControl                            = 0x00000000;
+SDRAM[0].McDisplaySnapRing                        = 0x00000003;
+SDRAM[0].McVideoProtectBom                        = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi                   = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb                     = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride                = 0xe4bac743;
+SDRAM[0].McVideoProtectVprOverride1               = 0x00000013;
+SDRAM[0].McVideoProtectGpuOverride0               = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1               = 0x00000000;
+SDRAM[0].McSecCarveoutBom                         = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi                       = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb                      = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess                = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess          = 0x00000000;
+SDRAM[0].EmcCaTrainingEnable                      = 0x00000000;
+SDRAM[0].EmcCaTrainingTimingCntl1                 = 0x1f7df7df;
+SDRAM[0].EmcCaTrainingTimingCntl2                 = 0x0000001f;
+SDRAM[0].SwizzleRankByteEncode                    = 0x0000006f;
+SDRAM[0].BootRomPatchControl                      = 0x00000000;
+SDRAM[0].BootRomPatchData                         = 0x00000000;
+SDRAM[0].McMtsCarveoutBom                         = 0xfff00000;
+SDRAM[0].McMtsCarveoutAdrHi                       = 0x00000000;
+SDRAM[0].McMtsCarveoutSizeMb                      = 0x00000000;
+SDRAM[0].McMtsCarveoutRegCtrl                     = 0x00000000;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c}          = 0x00000013;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960}           = 0x0000017c;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c}       = 0x00810038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380}       = 0x00810038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390}       = 0x0081003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8}     = 0x00810090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc}    = 0x00810041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0}      = 0x00810090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4}    = 0x00810041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344}       = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348}       = 0x00810080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320}     = 0x00810004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324}   = 0x00810004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310}         = 0x00080016;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314}         = 0x00000081;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4}       = 0x00810004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac}        = 0x00810019;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328}      = 0x00810018;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318}        = 0x00810024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394}        = 0x0081001c;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398}        = 0x00000081;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370}       = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374}       = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384}      = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388}      = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354}        = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358}        = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c}        = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360}        = 0x00810081;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350}       = 0x00810065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0}        = 0x0081001c;
diff --git a/src/mainboard/google/nyan/bct/sdram.cfg b/src/mainboard/google/nyan/bct/sdram-924.cfg
index fa3271a160..fa3271a160 100644
--- a/src/mainboard/google/nyan/bct/sdram.cfg
+++ b/src/mainboard/google/nyan/bct/sdram-924.cfg
diff --git a/src/mainboard/google/nyan/boardid.c b/src/mainboard/google/nyan/boardid.c
new file mode 100644
index 0000000000..18d920b6f5
--- /dev/null
+++ b/src/mainboard/google/nyan/boardid.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra124/gpio.h>
+
+#include "boardid.h"
+
+uint8_t board_id(void)
+{
+	static int id = -1;
+
+	if (id < 0) {
+		id = gpio_get_in_value(GPIO(Q3)) << 0 |
+		     gpio_get_in_value(GPIO(T1)) << 1 |
+		     gpio_get_in_value(GPIO(X1)) << 2 |
+		     gpio_get_in_value(GPIO(X4)) << 3;
+		printk(BIOS_SPEW, "Board ID: %#x.\n", id);
+	}
+
+	return id;
+}
diff --git a/src/mainboard/google/nyan/boardid.h b/src/mainboard/google/nyan/boardid.h
new file mode 100644
index 0000000000..b65f54337e
--- /dev/null
+++ b/src/mainboard/google/nyan/boardid.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_NYAN_BOARDID_H__
+#define __MAINBOARD_GOOGLE_NYAN_BOARDID_H__
+
+#include <stdint.h>
+
+uint8_t board_id(void);
+
+#endif /* __MAINBOARD_GOOGLE_NYAN_BOARDID_H__ */
diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c
index ca8eca42da..0761aedb7b 100644
--- a/src/mainboard/google/nyan/bootblock.c
+++ b/src/mainboard/google/nyan/bootblock.c
@@ -25,6 +25,7 @@
 #include <soc/clock.h>
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/clk_rst.h>
+#include <soc/nvidia/tegra124/gpio.h>
 #include <soc/nvidia/tegra124/pinmux.h>
 #include <soc/nvidia/tegra124/spi.h>	/* FIXME: move back to soc code? */
 
@@ -41,6 +42,10 @@ static void set_clock_sources(void)
 
 	/* TODO: is the 1.333MHz correct? This may have always been bogus... */
 	clock_configure_source(i2c5, CLK_M, 1333);
+
+	/* TODO: We should be able to set this to 50MHz, but that did not seem
+	 * reliable. */
+	clock_configure_source(sbc4, PLLP, 33333);
 }
 
 void bootblock_mainboard_init(void)
@@ -49,7 +54,13 @@ void bootblock_mainboard_init(void)
 
 	clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
 				 CLK_H_I2C5 | CLK_H_APBDMA,
-				 0, CLK_V_MSELECT, 0);
+				 0, CLK_V_MSELECT, 0, 0);
+
+	// Board ID GPIOs, bits 0-3.
+	gpio_input(GPIO(Q3));
+	gpio_input(GPIO(T1));
+	gpio_input(GPIO(X1));
+	gpio_input(GPIO(X4));
 
 	// I2C5 (PMU) clock.
 	pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index 623c5a196c..58945568e9 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -26,9 +26,11 @@ chip soc/nvidia/tegra124
 # are no single-access resources such as the infamous
 # cf8/cfc registers found on PCs.
 	register "display_controller" = "TEGRA_ARM_DISPLAYA"
-	register "xres" = "2560"
-	register "yres" = "1700"
-	register "framebuffer_bits_per_pixel" = "24"
+	register "xres" = "1366"
+	register "yres" = "768"
+	# this setting is what nvidia does; it makes no sense
+	# and does not agree with hardware. Why'd they do it?
+	register "framebuffer_bits_per_pixel" = "18"
 	register "cache_policy" = "DCACHE_WRITETHROUGH"
 
 	# With some help from the mainbaord designer
@@ -57,14 +59,22 @@ chip soc/nvidia/tegra124
 #V sync = 1713 - 1703 = 10
 #V back porch = 1749 - 1713 = 36
 #href_to_sync and vref_to_sync are from the vendor
-
-	register "href_to_sync" = "11"
-	register "hfront_porch" = "48"
-	register "hsync_width" = "32"
-	register "hback_porch" = "80"
+#this is just an example for a Pixel panel; other panels differ.
+# Here is a peppy panel:
+#  1366x768 (0x45)   76.4MHz -HSync -VSync *current +preferred
+#        h: width  1366 start 1502 end 1532 total 1592
+#        v: height  768 start  776 end  788 total  800
+# These numbers were provided by Nvidia.
+	register "href_to_sync" = "1"
+	register "hfront_porch" = "44"
+	register "hsync_width" = "46"
+	register "hback_porch" = "44"
 
 	register "vref_to_sync" = "1"
-	register "vfront_porch" = "3"
-	register "vsync_width" = "10"
-	register "vback_porch" = "36"
+	register "vfront_porch" = "6"
+	register "vsync_width" = "8"
+	register "vback_porch" = "6"
+
+	# we *know* the pixel clock for this system.
+	register "pixel_clock" = "71"
 end
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
index a25c91cf5d..1229e7485f 100644
--- a/src/mainboard/google/nyan/mainboard.c
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -25,6 +25,7 @@
 #include <soc/nvidia/tegra/i2c.h>
 #include <soc/nvidia/tegra124/clk_rst.h>
 #include <soc/nvidia/tegra124/gpio.h>
+#include <soc/nvidia/tegra124/mc.h>
 #include <soc/nvidia/tegra124/pmc.h>
 #include <soc/nvidia/tegra124/spi.h>
 #include <soc/nvidia/tegra124/usb.h>
@@ -48,15 +49,24 @@ static void set_clock_sources(void)
 	clock_configure_source(sdmmc3, PLLP, 48000);
 	clock_configure_source(sdmmc4, PLLP, 48000);
 
-	/* PLLP and PLLM are switched for HOST1x for no apparent reason. */
-	write32(4 /* PLLP! */ << CLK_SOURCE_SHIFT |
-		/* TODO(rminnich): The divisor isn't accurate enough to get to
-		 * 144MHz (it goes to 163 instead). What should we do here? */
-		CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000),
-		&clk_rst->clk_src_host1x);
+	/* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
+	 * Note the source id of CLK_M for EXTPERIPH1 is 3. */
+	clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
+
+	/*
+	 * I2S1 can use either PLLP or PLLA. Using PLLP is sufficient now since
+	 * we only need 4.8MHz. Note the source id of PLLP for I2S is 4.
+	 */
+	clock_configure_irregular_source(i2s1, PLLP, 4800, 4);
+
+	/* Note source id of PLLP for HOST1x is 4. */
+	clock_configure_irregular_source(host1x, PLLP, 408000, 4);
+
+	/* Use PLLD_OUT0 as clock source for disp1 */
+	clrsetbits_le32(&clk_rst->clk_src_disp1,
+			CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+			2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
 
-	/* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */
-	clock_configure_source(disp1, PLLC, 600000);
 }
 
 static void setup_pinmux(void)
@@ -74,6 +84,9 @@ static void setup_pinmux(void)
 	// EC in RW.
 	gpio_input_pullup(GPIO(U4));
 
+	// SOC and TPM reset GPIO, active low.
+	gpio_output(GPIO(I5), 1);
+
 	// SPI1 MOSI
 	pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
 						 PINMUX_PULL_UP |
@@ -169,10 +182,25 @@ static void setup_pinmux(void)
 	pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
 			  PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
 
-	/* TODO: This is supposed to work with the USB special function pinmux,
-	 * but it doesn't. Go with GPIOs for now and solve the problem later. */
-	gpio_output_open_drain(GPIO(N4), 1);	/* USB VBUS EN0 */
-	gpio_output_open_drain(GPIO(N5), 1);	/* USB VBUS EN1 */
+	/* We pull the USB VBUS signals up but keep them as inputs since the
+	 * voltage source likes to drive them low on overcurrent conditions */
+	gpio_input_pullup(GPIO(N4));	/* USB VBUS EN0 */
+	gpio_input_pullup(GPIO(N5));	/* USB VBUS EN1 */
+
+	/* Clock output 1 (for external peripheral) */
+	pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
+			  PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
+
+	/* I2S1 */
+	pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
+			  PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_TRISTATE |
+			  PINMUX_INPUT_ENABLE);
+	pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
+			  PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
+	pinmux_set_config(PINMUX_DAP2_FS_INDEX,
+			  PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
+	pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
+			  PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 }
 
 static void setup_kernel_info(void)
@@ -185,6 +213,12 @@ static void setup_kernel_info(void)
 	// value defined in BCT.
 	struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
 	writel(0x80080000, &pmc->odmdata);
+
+	// Not strictly info, but kernel graphics driver needs this region locked down
+	struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
+	writel(0, &mc->mc_vpr_bom);
+	writel(0, &mc->mc_vpr_size);
+	writel(1, &mc->mc_vpr_ctrl);
 }
 
 static void setup_ec_spi(void)
@@ -201,13 +235,35 @@ static void setup_ec_spi(void)
 static void mainboard_init(device_t dev)
 {
 	set_clock_sources();
-	clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 |
-				 CLK_L_SDMMC4 | CLK_L_USBD,
+
+	clock_external_output(1); /* For external MAX98090 audio codec. */
+
+	/*
+	 * Confirmed by NVIDIA hardware team, we need to take ALL audio devices
+	 * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
+	 * of reset and clock-enabled, otherwise reading AHUB devices (In our
+	 * case, I2S/APBIF/AUDIO<XBAR>) will hang.
+	 */
+	clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
+				 CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
+				 CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
+				 CLK_L_HOST1X,
+
 				 CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
 				 CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
+
 				 CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
-				 CLK_V_I2C4,
-				 CLK_W_DVFS);
+
+				 CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
+				 CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
+				 CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
+
+				 CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
+
+				 CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
+				 CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
+				 CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
+				 CLK_X_AFC5);
 
 	usb_setup_utmip1();
 	/* USB2 is the camera, we don't need it in firmware */
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c
index f52a48b8af..e63d9f7e24 100644
--- a/src/mainboard/google/nyan/pmic.c
+++ b/src/mainboard/google/nyan/pmic.c
@@ -23,36 +23,76 @@
 #include <stdint.h>
 #include <stdlib.h>
 
+#include "boardid.h"
 #include "pmic.h"
 
-struct pmic_write
-{
-	uint8_t reg; // Register to write.
-	uint8_t val; // Value to write.
-};
-
 enum {
 	AS3722_I2C_ADDR = 0x40
 };
 
-static struct pmic_write pmic_writes[] =
+struct as3722_init_reg {
+	u8 reg;
+	u8 val;
+};
+
+static struct as3722_init_reg init_list[] = {
+	{AS3722_SDO0, 0x3C},
+	{AS3722_SDO1, 0x32},
+	{AS3722_SDO2, 0x3C},
+	{AS3722_SDO3, 0x00},
+	{AS3722_SDO4, 0x00},
+	{AS3722_SDO5, 0x50},
+	{AS3722_SDO6, 0x28},
+	{AS3722_LDO0, 0x8A},
+	{AS3722_LDO1, 0x00},
+	{AS3722_LDO2, 0x10},
+	{AS3722_LDO3, 0x59},
+	{AS3722_LDO4, 0x00},
+	{AS3722_LDO5, 0x00},
+	{AS3722_LDO6, 0x3F},
+	{AS3722_LDO7, 0x00},
+	{AS3722_LDO9, 0x00},
+	{AS3722_LDO10, 0x00},
+	{AS3722_LDO11, 0x00},
+};
+#define AS3722_INIT_REG_LEN ARRAY_SIZE(init_list)
+
+static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val)
 {
-	/* Don't need to set up VDD_CORE - already done - by OTP */
+	i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
+	udelay(10 * 1000);
+}
 
-	/* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */
-	{ 0x00, 0x28 },
+static void pmic_slam_defaults(unsigned bus)
+{
+	int i;
 
-	/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+	for (i = 0; i < AS3722_INIT_REG_LEN; i++)
+		pmic_write_reg(bus, init_list[i].reg, init_list[i].val);
+}
 
-	/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
-	{ 0x06, 0x28 },
+void pmic_init(unsigned bus)
+{
+	/*
+	 * Don't need to set up VDD_CORE - already done - by OTP
+	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
+	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
+	 */
 
-	/* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */
+	/* Restore PMIC POR defaults, in case kernel changed 'em */
+	pmic_slam_defaults(bus);
 
-	/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
-	{ 0x12, 0x10 },
+	/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
+	if (board_id() == 0)
+		pmic_write_reg(bus, 0x00, 0x3c);
+	else
+		pmic_write_reg(bus, 0x00, 0x50);
 
-	/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
+	/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
+	pmic_write_reg(bus, 0x06, 0x28);
+
+	/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
+	pmic_write_reg(bus, 0x12, 0x10);
 
 	/*
 	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
@@ -61,23 +101,12 @@ static struct pmic_write pmic_writes[] =
 	 * NOTE: We do this early because doing it later seems to hose the CPU
 	 * power rail/partition startup. Need to debug.
 	 */
-	{ 0x16, 0x3f },
+	pmic_write_reg(bus, 0x16, 0x3f);
 
-	/* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */
-	/* panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
+	/*
+	 * Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
 	 * the value (register 0x20 bit 4)
 	 */
-	{ 0x0c, 0x07 },
-	{ 0x20, 0x10 },
-};
-
-void pmic_init(unsigned bus)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) {
-		i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1,
-			  &pmic_writes[i].val, 1);
-		udelay(10 * 1000);
-	}
+	pmic_write_reg(bus, 0x0c, 0x07);
+	pmic_write_reg(bus, 0x20, 0x10);
 }
diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h
index 78c9f0d7f2..dd65808e57 100644
--- a/src/mainboard/google/nyan/pmic.h
+++ b/src/mainboard/google/nyan/pmic.h
@@ -20,6 +20,29 @@
 #ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__
 #define __MAINBOARD_GOOGLE_NYAN_PMIC_H__
 
+enum {
+	AS3722_SDO0 = 0,
+	AS3722_SDO1,
+	AS3722_SDO2,
+	AS3722_SDO3,
+	AS3722_SDO4,
+	AS3722_SDO5,
+	AS3722_SDO6,
+
+	AS3722_LDO0 = 0x10,
+	AS3722_LDO1,
+	AS3722_LDO2,
+	AS3722_LDO3,
+	AS3722_LDO4,
+	AS3722_LDO5,
+	AS3722_LDO6,
+	AS3722_LDO7,
+
+	AS3722_LDO9 = 0x19,
+	AS3722_LDO10,
+	AS3722_LDO11,
+};
+
 void pmic_init(unsigned bus);
 
 #endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index a31f1f1519..e7895566f9 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -27,6 +27,7 @@
 #include <console/console.h>
 #include "soc/nvidia/tegra124/chip.h"
 #include <soc/display.h>
+#include <timestamp.h>
 
 // Convenient shorthand (in MB)
 #define DRAM_START	(CONFIG_SYS_SDRAM_BASE >> 20)
@@ -73,6 +74,10 @@ static void configure_l2actlr(void)
 
 void main(void)
 {
+#if CONFIG_COLLECT_TIMESTAMPS
+	uint64_t romstage_start_time = timestamp_get();
+#endif
+
 	// Globally disable MMU, caches and branch prediction (these should
 	// already be disabled by default on reset).
 	uint32_t sctlr = read_sctlr();
@@ -89,6 +94,8 @@ void main(void)
 	configure_l2ctlr();
 	configure_l2actlr();
 
+	console_init();
+
 	mmu_init();
 	mmu_config_range(0, DRAM_START, DCACHE_OFF);
 	mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
@@ -101,12 +108,15 @@ void main(void)
 
 	exception_init();
 
-	/* for quality of the user interface, it's important to get
+	/* For quality of the user experience, it's important to get
 	 * the video going ASAP. Because there are long delays in some
 	 * of the powerup steps, we do some very early setup here in
-	 * romstage. We don't do this in the bootblock because video
-	 * setup is finicky and subject to change; hence, we do it as
-	 * early as we can in the RW stage, but never in the RO stage.
+	 * romstage. The only thing setup_display does is manage
+	 * 4 GPIOs, under control of the config struct members.
+	 * In general, it is safe to enable panel power, and disable
+	 * anything related to the backlight. If we get something wrong,
+	 * we can easily fix it in ramstage by further GPIO manipulation,
+	 * so we feel it is ok to do some setting at this point.
 	 */
 
 	const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
@@ -119,7 +129,15 @@ void main(void)
 
 	cbmem_initialize_empty();
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(0);
+	timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
+	timestamp_add(TS_START_COPYRAM, timestamp_get());
+#endif
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
 				      "fallback/coreboot_ram");
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add(TS_END_COPYRAM, timestamp_get());
+#endif
 	stage_exit(entry);
 }