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authorDuncan Laurie <dlaurie@chromium.org>2017-01-21 16:57:57 -0800
committerDuncan Laurie <dlaurie@chromium.org>2017-01-22 19:25:04 +0100
commite00365217cf30c7b8510fca0e7e60d0905b73752 (patch)
treede0bdb9806fa9504994a5677bfdd34cb1a8b03fe /src/mainboard
parent4234ca276419314a0df598c7375c683def67ab1a (diff)
google/eve: Enable separate recovery MRC cache
In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/eve/Kconfig2
-rw-r--r--src/mainboard/google/eve/chromeos.fmd31
2 files changed, 20 insertions, 13 deletions
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index 32c029d192..e83e7d96a0 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -18,7 +18,9 @@ config BOARD_SPECIFIC_OPTIONS
config CHROMEOS
select EC_GOOGLE_CHROMEEC_SWITCHES
+ select HAS_RECOVERY_MRC_CACHE
select LID_SWITCH
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config DRIVERS_I2C_GENERIC
def_bool y
diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd
index 58b612781f..bdadcf728d 100644
--- a/src/mainboard/google/eve/chromeos.fmd
+++ b/src/mainboard/google/eve/chromeos.fmd
@@ -4,24 +4,29 @@ FLASH@0xff000000 0x1000000 {
SI_ME@0x1000 0x1ff000
}
SI_BIOS@0x200000 0xe00000 {
- RW_SECTION_A@0x0 0x3f0000 {
+ RW_SECTION_A@0x0 0x3e8000 {
VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x3dffc0
- RW_FWID_A@0x3effc0 0x40
+ FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
+ RW_FWID_A@0x3e7fc0 0x40
}
- RW_SECTION_B@0x3f0000 0x3f0000 {
+ RW_SECTION_B@0x3e8000 0x3e8000 {
VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x3dffc0
- RW_FWID_B@0x3effc0 0x40
+ FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
+ RW_FWID_B@0x3e7fc0 0x40
}
- RW_MRC_CACHE@0x7e0000 0x10000
- RW_ELOG@0x7f0000 0x4000
- RW_SHARED@0x7f4000 0x4000 {
- SHARED_DATA@0x0 0x2000
- VBLOCK_DEV@0x2000 0x2000
+ RW_MISC@0x7d0000 0x30000 {
+ UNIFIED_MRC_CACHE@0x0 0x20000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ }
+ RW_ELOG@0x20000 0x4000
+ RW_SHARED@0x24000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x28000 0x2000
+ RW_NVRAM@0x2a000 0x6000
}
- RW_VPD@0x7f8000 0x2000
- RW_NVRAM@0x7fa000 0x6000
RW_LEGACY(CBFS)@0x800000 0x200000
WP_RO@0xa00000 0x400000 {
RO_VPD@0x0 0x4000