mainboard/amenia: add the inital files for amenia board

Add amenia board files

Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/14352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

13 files changed, 617 insertions, 0 deletions

diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig
new file mode 100644
index 0000000000..f1946b5c09
--- /dev/null
+++ b/src/mainboard/intel/amenia/Kconfig
@@ -0,0 +1,53 @@
+if BOARD_INTEL_AMENIA
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_INTEL_APOLLOLAKE
+	select BOARD_ROMSIZE_KB_8192
+	select MAINBOARD_HAS_CHROMEOS
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_LPC_TPM
+	select HAVE_ACPI_RESUME
+	select MAINBOARD_HAS_CHROMEOS
+
+config CHROMEOS
+	bool
+	default y
+
+config MAINBOARD_DIR
+	string
+	default intel/amenia
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Amenia"
+
+config MAINBOARD_VENDOR
+	string
+	default "Intel"
+
+config FMAP_FILE
+	string
+	default "amenia"
+
+config PREBUILT_SPI_IMAGE
+	string
+	default "amenia.bin.orig.a0"
+
+config IFD_BIOS_END
+	hex
+	default 0x6FF000
+
+config IFD_BIOS_START
+	hex
+	default 0x1000
+
+config FLASHMAP_OFFSET
+	hex
+	default 0x200000
+
+config MAX_CPUS
+	int
+	default 8
+
+endif # BOARD_INTEL_AMENIA
diff --git a/src/mainboard/intel/amenia/Kconfig.name b/src/mainboard/intel/amenia/Kconfig.name
new file mode 100644
index 0000000000..ab2768843f
--- /dev/null
+++ b/src/mainboard/intel/amenia/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_INTEL_AMENIA
+	bool "Amenia"
+
diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc
new file mode 100644
index 0000000000..00d738ee80
--- /dev/null
+++ b/src/mainboard/intel/amenia/Makefile.inc
@@ -0,0 +1,5 @@
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c
diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl
new file mode 100644
index 0000000000..76c63b725f
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi/mainboard.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs.h>
+
+Scope (\_SB.PCI0.I2C4)
+{
+	Device (ETPA)
+	{
+		Name (_HID, "ELAN0000")
+		Name (_DDN, "Elan Touchpad")
+		Name (_UID, 1)
+		Name (ISTP, 1) /* Touchpad */
+
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x15,                     // SlaveAddress
+				ControllerInitiated,      // SlaveMode
+				400000,                   // ConnectionSpeed
+				AddressingMode7Bit,       // AddressingMode
+				"\\_SB.PCI0.I2C4",        // ResourceSource
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				GPIO_18_IRQ
+			}
+		})
+
+		Method (_STA)
+		{
+				Return (0xF)
+		}
+
+	}
+}
diff --git a/src/mainboard/intel/amenia/acpi_tables.c b/src/mainboard/intel/amenia/acpi_tables.c
new file mode 100644
index 0000000000..9a9cc3a895
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi_tables.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	memset(fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 5;
+	memcpy(header->oem_id, OEM_ID, ARRAY_SIZE(header->oem_id));
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, ARRAY_SIZE(header->oem_table_id));
+	memcpy(header->asl_compiler_id, ASLC, ARRAY_SIZE(header->asl_compiler_id));
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (uintptr_t)facs;
+	fadt->dsdt = (uintptr_t)dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->x_firmware_ctl_l = (uintptr_t)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (uintptr_t)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	soc_fill_common_fadt(fadt);
+
+	header->checksum = acpi_checksum((void *)fadt, header->length);
+}
diff --git a/src/mainboard/intel/amenia/board_info.txt b/src/mainboard/intel/amenia/board_info.txt
new file mode 100644
index 0000000000..b97ca1518d
--- /dev/null
+++ b/src/mainboard/intel/amenia/board_info.txt
@@ -0,0 +1,4 @@
+Vendor name: Intel
+Board name: Amenia Board
+Category: eval
+Flashrom support: y
diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c
new file mode 100644
index 0000000000..dabb899e36
--- /dev/null
+++ b/src/mainboard/intel/amenia/chromeos.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <vendorcode/google/chromeos/chromeos.h>
+
+int get_lid_switch(void)
+{
+	/* Default to force open */
+	return 1;
+}
+
+/* The dev-switch is virtual */
+int get_developer_mode_switch(void)
+{
+	return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+int get_write_protect_state(void)
+{
+	return 0;
+}
diff --git a/src/mainboard/intel/amenia/chromeos.fmd b/src/mainboard/intel/amenia/chromeos.fmd
new file mode 100644
index 0000000000..9c60c8023c
--- /dev/null
+++ b/src/mainboard/intel/amenia/chromeos.fmd
@@ -0,0 +1,37 @@
+FLASH 8M {
+    WP_RO 4M {
+        SI_ALL 2M {
+            SI_DESC 4K
+            bootblock@509056 32K
+        }
+        RO_SECTION@2M 2M {
+            FMAP 2K
+            RO_FRID 0x40
+            RO_VPD @4K 16K
+            COREBOOT(CBFS)
+            SIGN_CSE@0x180000 64K
+            GBB
+        }
+    }
+    MISC_RW  {
+        RW_MRC_CACHE 64K
+        RW_ELOG 16K
+        RW_SHARED 16K {
+            SHARED_DATA 8K
+            VBLOCK_DEV 8K
+        }
+        RW_VPD 8K
+    }
+    RW_SECTION_A 0xf0000 {
+        VBLOCK_A 64K
+        FW_MAIN_A(CBFS) 768K
+        RW_FWID_A 64
+    }
+    RW_SECTION_B 0xf0000 {
+        VBLOCK_B 64K
+        FW_MAIN_B(CBFS) 768K
+        RW_FWID_B 64
+    }
+    DEVICE_EXTENSION@7M 1M
+}
+
diff --git a/src/mainboard/intel/amenia/chromeos_ramstage.c b/src/mainboard/intel/amenia/chromeos_ramstage.c
new file mode 100644
index 0000000000..dcc6b90010
--- /dev/null
+++ b/src/mainboard/intel/amenia/chromeos_ramstage.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, 0, "write protect"},
+		{-1, ACTIVE_HIGH, 0, "recovery"},
+		{-1, ACTIVE_HIGH, 1, "developer"},
+		{-1, ACTIVE_HIGH, 1, "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, 0, "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
new file mode 100644
index 0000000000..c54e838826
--- /dev/null
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -0,0 +1,52 @@
+chip soc/intel/apollolake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	register "pcie_rp0_clkreq_pin" = "3"    # wifi/bt
+	register "pcie_rp2_clkreq_pin" = "0"    # SSD
+
+	device domain 0 on
+		device pci 00.0 on end	# - Host Bridge
+		device pci 00.1 on end	# - DPTF
+		device pci 00.2 on end	# - NPK
+		device pci 02.0 on end	# - Gen
+		device pci 03.0 on end	# - Iunit
+		device pci 0d.0 on end	# - P2SB
+		device pci 0d.1 on end	# - PMC
+		device pci 0d.2 on end	# - SPI
+		device pci 0d.3 on end	# - Shared SRAM
+		device pci 0e.0 on end	# - Audio
+		device pci 11.0 on end	# - ISH
+		device pci 12.0 on end	# - SATA
+		device pci 13.0 on end	# - PCIe-A 0
+		device pci 13.2 on end	# - Onboard Lan
+		device pci 13.3 on end	# - PCIe-A 3
+		device pci 14.0 on end	# - PCIe-B 0
+		device pci 14.1 on end	# - Onboard M2 Slot(Wifi/BT)
+		device pci 15.0 on end	# - XHCI
+		device pci 15.1 on end	# - XDCI
+		device pci 16.0 on end	# - I2C 0
+		device pci 16.1 on end	# - I2C 1
+		device pci 16.2 on end	# - I2C 2
+		device pci 16.3 on end	# - I2C 3
+		device pci 17.0 on end	# - I2C 4
+		device pci 17.1 on end	# - I2C 5
+		device pci 17.2 on end	# - I2C 6
+		device pci 17.3 on end	# - I2C 7
+		device pci 18.0 on end	# - UART 0
+		device pci 18.1 on end	# - UART 1
+		device pci 18.2 on end	# - UART 2
+		device pci 18.3 on end	# - UART 3
+		device pci 19.0 on end	# - SPI 0
+		device pci 19.1 on end	# - SPI 1
+		device pci 19.2 on end	# - SPI 2
+		device pci 1a.0 on end	# - PWM
+		device pci 1b.0 on end	# - SDCARD
+		device pci 1c.0 on end	# - eMMC
+		device pci 1e.0 on end	# - SDIO
+		device pci 1f.0 on end	# - LPC
+		device pci 1f.1 on end	# - SMBUS
+	end
+end
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
new file mode 100644
index 0000000000..ba4e7226fc
--- /dev/null
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+                #include <soc/intel/apollolake/acpi/northbridge.asl>
+                #include <soc/intel/apollolake/acpi/southbridge.asl>
+		}
+	}
+	/* Mainboard Specific devices */
+	#include "acpi/mainboard.asl"
+
+        /* Chipset specific sleep states */
+        #include <soc/intel/apollolake/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c
new file mode 100644
index 0000000000..9949061347
--- /dev/null
+++ b/src/mainboard/intel/amenia/mainboard.c
@@ -0,0 +1,143 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <soc/gpio.h>
+
+/* TODO: Move GPIO config to its own file once we get more GPIOs in the list */
+static const struct pad_config amenia_gpios[] = {
+	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),		/* UART2 RX*/
+	PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1),		/* UART2 TX*/
+	PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1),	/* PANEL0_VDDEN */
+	PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1),	/* PANEL0_BKLTEN */
+	PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1),	/* PANEL0_BKLTCTL */
+
+	PAD_CFG_GPI(GPIO_9, UP_20K, DEEP),		/* SPI_TPM_IRQ_N  */
+	PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE),	/* SOC_WAKE_SCI_N */
+	PAD_CFG_GPI_APIC(GPIO_18, UP_20K, DEEP, LEVEL, NONE),	/* Trackpad_INT_N */
+	PAD_CFG_GPI_APIC(GPIO_19, UP_20K, DEEP, LEVEL, NONE),	/* Audio_Jack_Present_N */
+	PAD_CFG_GPI_APIC(GPIO_21, UP_20K, DEEP, LEVEL, NONE),	/* TCH_INT_N */
+	PAD_CFG_GPI_APIC(GPIO_22, UP_20K, DEEP, LEVEL, NONE),	/* EC_SOC_WAKE_1P8_N */
+	PAD_CFG_GPO(GPIO_23, 1, DEEP),			/* GPS_NSTANDBY */
+	PAD_CFG_GPO(GPIO_24, 1, DEEP),			/* SSD_SATA_DEVSLP */
+	PAD_CFG_GPI_APIC(GPIO_30, UP_20K, DEEP, LEVEL, NONE),	/* EC_KBD_IRQ_SOC_N */
+	PAD_CFG_NF(GPIO_32, NATIVE, DEEP, NF5),		/* GPS_SUSCLK_32K */
+	PAD_CFG_GPI(GPIO_33, UP_20K, DEEP),		/* EC_KBD_IRQ_SOC_N */
+	PAD_CFG_GPO(GPIO_36, 0, DEEP),			/* TOUCH_PNL_RST */
+	PAD_CFG_NF(GPIO_37, NATIVE, DEEP, NF1),		/* SOC_BUZZER */
+	PAD_CFG_GPI(GPIO_41, UP_20K, DEEP),		/* LPSS_UART0_CTS_B */
+
+	PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),		/* GPS_UART_RXD */
+	PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),		/* GPS_UART_TXD */
+	PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1),		/* GPS_UART_RTS_B */
+	PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1),		/* GPS_UART_CTS_N */
+
+	PAD_CFG_GPI_SMI(GPIO_49, UP_20K, DEEP, LEVEL, NONE),	/* EC_SMI_N */
+	PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),		/* SPI_WP_STAT */
+
+	PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1),		/* DMIC_CLK_A1 */
+	PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1),		/* DMIC_CLK_B1 */
+	PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1),		/* DMIC_DATA_1 */
+	PAD_CFG_NF(GPIO_82, NATIVE, DEEP, NF1),		/* DMIC_CLK_AB2 */
+	PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1),		/* DMIC_DATA_2 */
+	PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1),		/* MCLK */
+
+	PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1),		/* I2S2_BCLK_AMP */
+	PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1),		/* I2S2_SYNC_AMP */
+	PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1),		/* I2S2_SDI_AMP */
+	PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1),		/* I2S2_SDO_AMP */
+	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
+	PAD_CFG_GPI_APIC(GPIO_116, UP_20K, DEEP, LEVEL, INVERT),	/* AUDIO_CODEC_IRQ_N */
+
+	PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1),		/* I2C_SDA for Audio Codec */
+	PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1),		/* I2C_SCL for Audio Codec */
+
+	PAD_CFG_NF(GPIO_128, UP_5K, DEEP, NF1),		/* I2C_SDA for ALS */
+	PAD_CFG_NF(GPIO_129, UP_5K, DEEP, NF1),		/* I2C_SCL for ALS */
+
+	PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1),		/* I2C_SDA for Touch Screen */
+	PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1),		/* I2C_SCL for Touchscreen */
+
+	PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1),		/* I2C_SDA for Trackpad */
+	PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1),		/* I2C_SCL for Trackpad */
+
+	PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2),	/* I2S6_BCLK_Codec */
+	PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2),	/* I2S6_SYNC_Codec */
+	PAD_CFG_NF(GPIO_148, NATIVE, DEEP, NF2),	/* I2S6_SDI_Codec */
+	PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2),	/* I2S6_SDO_Codec */
+
+	PAD_CFG_GPO(GPIO_150, 1, DEEP),			/* WIFI_PERST_1P8_N */
+	PAD_CFG_GPI(GPIO_151, UP_20K, DEEP),		/* RSVD (ISH_BASE_ACCEL_INT_N) */
+	PAD_CFG_GPI(GPIO_152, UP_20K, DEEP),		/* RSVD (ALS_IRQ_N) */
+
+	PAD_CFG_GPO(GPIO_154, 1, DEEP),			/* BT_DISABLE_1P8_N */
+	PAD_CFG_GPI(GPIO_167, NONE, DEEP),		/* DB_ID */
+
+
+	PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1),	/* SDCARD_CLK */
+	PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1),	/* SDCARD_D0 */
+	PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1),	/* SDCARD_D1 */
+	PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1),	/* SDCARD_D2 */
+	PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),	/* SDCARD_D3 */
+	PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1),	/* SDCARD_CD_B */
+	PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),	/* SDCARD_CMD */
+	PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1),	/* SDCARD_CLK_FB */
+	PAD_CFG_GPO(GPIO_183, 1, DEEP),			/* SDCARD_PWR_EN_N */
+
+
+	/* Configure eMMC pins for proper pull UP/DN */
+	PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1),    /* EMMC0_CLK */
+	PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1),    /* EMMC0_D0 */
+	PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1),    /* EMMC0_D1 */
+	PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1),    /* EMMC0_D2 */
+	PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1),    /* EMMC0_D3 */
+	PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1),    /* EMMC0_D4 */
+	PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1),    /* EMMC0_D5 */
+	PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1),    /* EMMC0_D6 */
+	PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1),    /* EMMC0_D7 */
+	PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1),    /* EMMC0_CMD */
+	PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1),    /* EMMC_RCLK */
+
+	PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1),	/* DDI0_HPD */
+	PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1),	/* DDI1_HPD */
+
+	PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1),	/* USB2_OC0_3p3_N */
+	PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1),	/* USB2_OC2_N */
+
+	PAD_CFG_NF(GPIO_205, NATIVE, DEEP, NF1),	/* PCIE_WLAN_WAKE3_N */
+	PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1),	/* PCIE_SSD_WAKE0_N */
+	PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1),	/* SSD CLKREQ */
+	PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1),	/* Wifi CLKREQ */
+
+	PAD_CFG_GPO(PMU_BATLOW_B, 0, DEEP),		/* EMMC_PLTRST_N ?? */
+	PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1),	/* LPC_SERIRQ */
+	PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1),	/* LPC_CLKRUN_N */
+
+	PAD_CFG_NF(GPIO_199,NATIVE,DEEP,NF2),		/* HV_DDI1_HPD */
+	PAD_CFG_NF(GPIO_200,NATIVE,DEEP,NF2),		/* HV_DDI0_HPD */
+	PAD_CFG_NF(PMC_SPI_FS1,NATIVE,DEEP,NF2),	/* HV_DDI2_HPD */
+
+};
+
+static void mainboard_init(void *chip_info)
+{
+	gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios));
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c
new file mode 100644
index 0000000000..d08b343823
--- /dev/null
+++ b/src/mainboard/intel/amenia/romstage.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+#include <string.h>
+#include <soc/fsp/FspmUpd.h>
+
+/* Channel 0 PHY to DUnit DQ mapping */
+static const uint8_t swizzling_ch0_amenia[] = {
+	 9,  14,  12,  13,  10,  11,  8,  15,  7,  3, 5, 2, 6, 0, 1, 4,
+	28, 24, 26, 27, 29, 30, 31, 25, 20, 22, 23, 16, 19, 17, 18, 21,
+};
+
+/* Channel 1 PHY to DUnit DQ mapping */
+static const uint8_t swizzling_ch1_amenia[] = {
+	 6,  7,  5,  4,  3,  1,  0,  2,  12,  10, 11, 13, 14, 8, 9, 15,
+	16, 22, 23, 20, 18, 17, 19, 21, 30, 28, 29, 25, 24, 26, 27, 31,
+};
+
+/* Channel 2 PHY to DUnit DQ mapping */
+static const uint8_t swizzling_ch2_amenia[] = {
+	15,  9,  8, 11, 14, 13, 12, 10,  4,  3,  7,  5,  6,  1,  0,  2,
+	25, 28, 30, 31, 26, 27, 24, 29, 20, 23, 22, 21, 18, 19, 16, 17,
+};
+
+/* Channel 3 PHY to DUnit DQ mapping */
+static const uint8_t swizzling_ch3_amenia[] = {
+	 2,  1,  6,  7,  5,  4,  3,  0,  11,  10, 8, 9, 12, 15, 13, 14,
+	17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30,
+};
+
+static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg)
+{
+	cfg->Profile = 11;			/* 0xB:LPDDR4_2400_24_22_22 */
+	cfg->DIMM0SPDAddress = 0;
+	cfg->DIMM1SPDAddress = 0;
+	cfg->Ch0_RankEnable = 0x1;
+	cfg->Ch0_DeviceWidth = 0x1;
+	cfg->Ch0_DramDensity = 0x2;
+	cfg->Ch0_Option = 0x3;			/* Bank Address Hashing enabled */
+	cfg->Ch0_TristateClk1 = 0;
+	cfg->Ch0_Mode2N = 0;
+	cfg->Ch0_OdtLevels = 0;
+	cfg->Ch1_RankEnable = 0x1;
+	cfg->Ch1_DeviceWidth = 0x1;
+	cfg->Ch1_DramDensity = 0x2;
+	cfg->Ch1_Option = 0x3;			/* Bank Address Hashing enabled */
+	cfg->Ch1_TristateClk1 = 0;
+	cfg->Ch1_Mode2N = 0;
+	cfg->Ch1_OdtLevels = 0;
+	cfg->Ch2_RankEnable = 0x1;
+	cfg->Ch2_DeviceWidth = 0x1;
+	cfg->Ch2_DramDensity = 0x2;
+	cfg->Ch2_Option = 0x3;			/* Bank Address Hashing enabled */
+	cfg->Ch2_TristateClk1 = 0;
+	cfg->Ch2_Mode2N = 0;
+	cfg->Ch2_OdtLevels = 0;
+	cfg->Ch3_RankEnable = 0x1;
+	cfg->Ch3_DeviceWidth = 0x1;
+	cfg->Ch3_DramDensity = 0x2;
+	cfg->Ch3_Option = 0x3;			/* Bank Address Hashing enabled */
+	cfg->Ch3_TristateClk1 = 0;
+	cfg->Ch3_Mode2N = 0;
+	cfg->Ch3_OdtLevels = 0;
+
+	memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_amenia,
+	       sizeof(swizzling_ch0_amenia));
+	memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_amenia,
+	       sizeof(swizzling_ch1_amenia));
+	memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_amenia,
+	       sizeof(swizzling_ch2_amenia));
+	memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_amenia,
+	       sizeof(swizzling_ch3_amenia));
+}
+
+void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+{
+	struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
+
+	cfg->Package = 1;			/* 0x1:BGA */
+	cfg->MemoryDown = 1;
+	cfg->DDR3LPageSize = 0;
+	cfg->DDR3LASR = 0;
+	cfg->ScramblerSupport = 1;
+	cfg->ChannelHashMask = 0x36;
+	cfg->SliceHashMask = 0x9;
+	cfg->InterleavedMode = 2;
+	cfg->ChannelsSlicesEnable = 0;
+	cfg->MinRefRate2xEnable = 0;
+	cfg->DualRankSupportEnable = 1;
+	cfg->DisableFastBoot = 0;
+	cfg->RmtMode = 0;
+	cfg->RmtCheckRun = 0;
+	cfg->RmtMarginCheckScaleHighThreshold = 0;
+	cfg->MemorySizeLimit = 0x1800;		/* Limit to 6GB */
+	cfg->LowMemoryMaxValue = 0;
+	cfg->HighMemoryMaxValue = 0;
+
+	amenia_fill_memory_params(cfg);
+}