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authorDuncan Laurie <dlaurie@chromium.org>2015-01-18 14:14:17 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 20:17:28 +0200
commitba081ef50dd6cd62de1165e8315aca9b3a40c337 (patch)
tree2d5b1d18246335bb33022f4b81a37609b9d915ef /src/mainboard
parent35dc00f75b3345fda78df56fe29495eb5fdf5827 (diff)
samus: Adjust SATA Gen3 TX voltage amplitude
Reduce the SATA Gen3 TX voltage amplitude by 210mV based on the provided test results to help with SATA validation. BUG=chrome-os-partner:34121 BRANCH=samus TEST=build and boot on samus and ensure SATA is still working, firmware image will be provided for full validation. Change-Id: I574d2f457b7b6831a339602a4165e959a0e2ee7d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 9500ec152d8f9c90513811b1a92d1a8c155f514a Original-Change-Id: I233fa1a9a7f2877a97ef6834304680f82b958e82 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241800 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9496 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/samus/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index a511c27e9a..1d7d5a1033 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/broadwell
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
+ register "sata_port0_gen3_tx" = "0x72"
register "sio_acpi_mode" = "1"
# Set I2C0 to 1.8V