coreboot used to have two different "APIs" for memory accesses:

read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)

read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.

This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 26 insertions, 19 deletions

diff --git a/src/mainboard/amd/db800/cache_as_ram_auto.c b/src/mainboard/amd/db800/cache_as_ram_auto.c
index f0e37d7306..5ee6dbb748 100644
--- a/src/mainboard/amd/db800/cache_as_ram_auto.c
+++ b/src/mainboard/amd/db800/cache_as_ram_auto.c
@@ -19,6 +19,7 @@
  */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>
diff --git a/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c b/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
index 4679ab44f3..0b3721a5b7 100644
--- a/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
+++ b/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
@@ -19,6 +19,7 @@
  */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>
diff --git a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
index 4282449945..70fa935a8d 100644
--- a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
+++ b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
@@ -1,4 +1,5 @@
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c
index d1c438ba35..24a350b92b 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c
+++ b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c
@@ -19,6 +19,7 @@
  */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <device/pci_def.h>
diff --git a/src/mainboard/intel/eagleheights/auto.c b/src/mainboard/intel/eagleheights/auto.c
index 47043a9067..d928de5c56 100644
--- a/src/mainboard/intel/eagleheights/auto.c
+++ b/src/mainboard/intel/eagleheights/auto.c
@@ -133,22 +133,22 @@ void early_config(void) {
 	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
 
 	/* Disable watchdog */
-	gcs = readl(DEFAULT_RCBA + RCBA_GCS);
+	gcs = read32(DEFAULT_RCBA + RCBA_GCS);
 	gcs |= (1 << 5); /* No reset */
-	writel(gcs, DEFAULT_RCBA + RCBA_GCS);
+	write32(DEFAULT_RCBA + RCBA_GCS, gcs);
 
 	/* Configure PCIe port B as 4x */
-	rpc = readl(DEFAULT_RCBA + RCBA_RPC);
+	rpc = read32(DEFAULT_RCBA + RCBA_RPC);
 	rpc |= (3 << 0);
-	writel(rpc, DEFAULT_RCBA + RCBA_RPC);
+	write32(DEFAULT_RCBA + RCBA_RPC, rpc);
 
 	/* Disable Modem, Audio, PCIe ports 2/3/4 */
-	fd = readl(DEFAULT_RCBA + RCBA_FD);
+	fd = read32(DEFAULT_RCBA + RCBA_FD);
 	fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
-	writel(fd, DEFAULT_RCBA + RCBA_FD);
+	write32(DEFAULT_RCBA + RCBA_FD, fd);
 
 	/* Enable HPET */
-	writel((1 << 7), DEFAULT_RCBA + RCBA_HPTC);
+	write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
 
 	/* Improve interrupt routing
 	 * D31:F2 SATA        INTB# -> PIRQD
@@ -160,10 +160,10 @@ void early_config(void) {
 	 * D28:F0 PCIe Port 1 INTA# -> PIRQE
 	 */
 
-	writew(0x0230, DEFAULT_RCBA + RCBA_D31IR);
-	writew(0x3210, DEFAULT_RCBA + RCBA_D30IR);
-	writew(0x3237, DEFAULT_RCBA + RCBA_D29IR);
-	writew(0x3214, DEFAULT_RCBA + RCBA_D28IR);
+	write16(DEFAULT_RCBA + RCBA_D31IR, 0x0230);
+	write16(DEFAULT_RCBA + RCBA_D30IR, 0x3210);
+	write16(DEFAULT_RCBA + RCBA_D29IR, 0x3237);
+	write16(DEFAULT_RCBA + RCBA_D28IR, 0x3214);
 
 	/* Setup sata mode */
 	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 7f2ca352d2..ac72aa0714 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -234,10 +234,10 @@ void *smp_write_config_table(void *v)
 	/* PCIe Port B
 	 */
 	for(i = 0; i < 4; i++) {
-	  pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+	  pin = (read32(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
 	  if(pin > 0) {
 	    pin -= 1;
-	    route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+	    route = PIRQ_A + ((read16(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
 	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
 	  }
 	}
@@ -245,20 +245,20 @@ void *smp_write_config_table(void *v)
 	/* USB 1.1 : device 29, function 0, 1
 	 */
 	for(i = 0; i < 2; i++) {
-	  pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+	  pin = (read32(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
 	  if(pin > 0) {
 	    pin -= 1;
-	    route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+	    route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
 	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
 	  }
 	}
 
 	/* USB 2.0 : device 29, function 7
 	*/
-	pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+	pin = (read32(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
 	if(pin > 0) {
 	  pin -= 1;
-	  route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+	  route = PIRQ_A + ((read16(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
 	  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
 	}
 
@@ -267,10 +267,10 @@ void *smp_write_config_table(void *v)
 	   Performance counters : device 31 function 4
 	 */
 	for(i = 2; i < 5; i++) {
-	  pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+	  pin = (read32(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
 	  if(pin > 0) {
 	    pin -= 1;
-	    route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+	    route = PIRQ_A + ((read16(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
 	    smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
 	  }
 	}
diff --git a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
index 47645cee30..3884a27eb6 100644
--- a/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
+++ b/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
@@ -22,6 +22,7 @@
 /* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdlib.h>
 #include <stdint.h>
diff --git a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
index 0e3e2de553..9aeeb63bc6 100644
--- a/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
+++ b/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
@@ -22,6 +22,7 @@
 /* Based on cache_as_ram_auto.c from AMD's DB800 and DBM690T mainboards. */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdlib.h>
 #include <stdint.h>
diff --git a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
index 5d96118394..e4828151ff 100644
--- a/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
+++ b/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
@@ -18,6 +18,7 @@
  */
 
 #define ASSEMBLY 1
+#define __PRE_RAM__
 
 #include <stdint.h>
 #include <spd.h>