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authorLijian Zhao <lijian.zhao@intel.com>2018-12-13 09:12:34 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 06:24:27 +0000
commit9bf1d8f2761d3f83123222225aab2673cde466a7 (patch)
tree8631844fcbe60816bae7aae51587889e9a73b3b4 /src/mainboard
parent21046a33ef7d46e13f7ea3e4b7fae7aead499d14 (diff)
soc/intel/cannonlake: SATA and DMI power optimize
Expose the FSP interface to enable SATA and PCH side DMI power optimize options. Actual step executed in FSP, step defined in cannonlake pch BIOS spec(CDI# 570374). Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78 Reviewed-on: https://review.coreboot.org/c/30211 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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