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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-06-23 13:07:10 -0600
committerMartin Roth <martinroth@google.com>2017-07-27 21:32:26 +0000
commit6f174ee0dda132d1d8e18398a79ecba99094a068 (patch)
treecbf7974cc194188fb26f24e274c100f9378ac355 /src/mainboard
parenta9d3d65a924ce765a481337ca22d36f5ab351ced (diff)
google/kahlee: Update for single DIMM
Update for a single DIMM with an SPD at address A0. Change-Id: I646f079c99cbaffd7094773243600c3030308325 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19833 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/OemCustomize.c2
-rw-r--r--src/mainboard/google/kahlee/devicetree.cb4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 3893e5dbcb..2b3ac292f6 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -20,7 +20,7 @@
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
- NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/devicetree.cb
index bb672b29e6..2d2fe3fbc8 100644
--- a/src/mainboard/google/kahlee/devicetree.cb
+++ b/src/mainboard/google/kahlee/devicetree.cb
@@ -16,7 +16,7 @@ chip soc/amd/stoneyridge
register "spdAddrLookup" = "
{
- { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
+ { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
}"
device cpu_cluster 0 on
@@ -41,7 +41,7 @@ chip soc/amd/stoneyridge
device pci 12.0 on end # EHCI
device pci 14.0 on # SM
chip drivers/generic/generic # dimm 0-0-0
- device i2c 51 on end
+ device i2c 50 on end
end
end # SM
device pci 14.3 on end # LPC 0x790e