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authorAaron Durbin <adurbin@chromium.org>2014-07-10 12:50:27 -0500
committerMarc Jones <marc.jones@se-eng.com>2015-03-05 17:31:04 +0100
commit5626d8f59a4a70da4724e778a38e0fe6847fa5d8 (patch)
tree4df6904e61edce7d7216970cff7ff1371012b11c /src/mainboard
parent1b770fb4b5a83042a6007cd9d263bfdf078822ad (diff)
t132: bring up 64-bit denver core
The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/rush/Makefile.inc1
-rw-r--r--src/mainboard/google/rush/romstage.c29
2 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 6f4a7748ed..3c2b5da30f 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -33,6 +33,7 @@ bootblock-y += pmic.c
bootblock-y += reset.c
romstage-y += reset.c
+romstage-y += romstage.c
romstage-y += sdram_configs.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
new file mode 100644
index 0000000000..bb173c09d6
--- /dev/null
+++ b/src/mainboard/google/rush/romstage.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_configure_pmc(void)
+{
+}
+
+void mainboard_enable_vdd_cpu(void)
+{
+ /* VDD_CPU is already enabled in bootblock. */
+}