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authorShobhit Srivastava <shobhit.srivastava@intel.com>2015-10-09 17:05:16 +0530
committerMartin Roth <martinroth@google.com>2017-08-25 18:57:51 +0000
commit448e5a2810aa735e0a062296b79db8efce559631 (patch)
tree353ad60bcf55c17a61acb6000b8910b8fb9b12e6 /src/mainboard
parent5836bf23c61da45dc5f90d62a01d20d8d86f18c2 (diff)
google/cyan: Enable CA Mirror
Cherry-pick from Chromium commit e49deb1. Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is board specific. Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/cyan/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index 2f2b2df7de..0454650c68 100644
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/braswell
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "1"
+ register "PcdCaMirrorEn" = "0"
############################################################
# Set the parameters for SiliconInit