diff options
| author | peichao.wang <peichao.wang@bitland.corp-partner.google.com> | 2018-09-26 17:38:16 +0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-09-26 15:12:13 +0000 |
| commit | 3debb1fe87383f34552a6796ed6cb4d54470ba52 (patch) | |
| tree | 1fd8ac29674b41f0ea865e1201f22777f14b96ea /src/mainboard | |
| parent | 8383d3205baecb44eb85d00275007007ce4bc644 (diff) | |
mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz)
Need to tune I2C bus 6 clock frequency under the 400KHz
Bug=b:116543001
TEST=flash coreboot to the DUT and measure I2C bus 6 clock
frequency whether arrive to 399.1KHz
Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/octopus/variants/phaser/overridetree.cb | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index f2824d8874..2f6915e62a 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -1,5 +1,46 @@ chip soc/intel/apollolake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid |