src/superio/ite/it8772f: Separate mainboard from SIO at obj level

Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.

Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

3 files changed, 21 insertions, 20 deletions

diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c
index c367968f90..c90c8e7987 100644
--- a/src/mainboard/google/panther/romstage.c
+++ b/src/mainboard/google/panther/romstage.c
@@ -30,11 +30,11 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "gpio.h"
 #include "superio/ite/it8772f/it8772f.h"
-#include "superio/ite/it8772f/early_serial.c"
 #include "superio/ite/common/ite.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 
 const struct rcba_config_instruction rcba_config[] = {
@@ -145,7 +145,7 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	/* Early SuperIO setup */
 	ite_kill_watchdog(GPIO_DEV);
-	it8772f_ac_resume_southbridge();
+	it8772f_ac_resume_southbridge(DUMMY_DEV);
 	pch_enable_lpc();
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 6ab7007dbb..153ce5c68b 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -34,8 +34,6 @@
 #include <bootmode.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8772f/it8772f.h>
-/* FIXME: SUPERIO include.c */
-#include "superio/ite/it8772f/early_serial.c"
 #include "northbridge/intel/sandybridge/sandybridge.h"
 #include "northbridge/intel/sandybridge/raminit.h"
 #include "southbridge/intel/bd82x6x/pch.h"
@@ -61,6 +59,7 @@
 #endif
 #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */
 
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
 
@@ -148,29 +147,29 @@ static void setup_sio_gpios(void)
 	 * GPIO10 as USBPWRON12#
 	 * GPIO12 as USBPWRON13#
 	 */
-	it8772f_gpio_setup(1, 0x05, 0x05, 0x00, 0x05, 0x05);
+	it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05);
 
 	/*
 	 * GPIO22 as wake SCI#
 	 */
-	it8772f_gpio_setup(2, 0x04, 0x04, 0x00, 0x04, 0x04);
+	it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04);
 
 	/*
 	 * GPIO32 as EXTSMI#
 	 */
-	it8772f_gpio_setup(3, 0x04, 0x04, 0x00, 0x04, 0x04);
+	it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04);
 
 	/*
 	 * GPIO45 as LED_POWER#
 	 */
-	it8772f_gpio_setup(4, 0x20, 0x20, 0x20, 0x20, 0x20);
+	it8772f_gpio_setup(DUMMY_DEV, 4, 0x20, 0x20, 0x20, 0x20, 0x20);
 
 	/*
 	 * GPIO51 as USBPWRON8#
 	 * GPIO52 as USBPWRON1#
 	 */
-	it8772f_gpio_setup(5, 0x06, 0x06, 0x00, 0x06, 0x06);
-	it8772f_gpio_setup(6, 0x00, 0x00, 0x00, 0x00, 0x00);
+	it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06);
+	it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00);
 }
 
 void main(unsigned long bist)
@@ -239,7 +238,7 @@ void main(unsigned long bist)
 	setup_sio_gpios();
 
 	/* Early SuperIO setup */
-	it8772f_ac_resume_southbridge();
+	it8772f_ac_resume_southbridge(DUMMY_DEV);
 	ite_kill_watchdog(GPIO_DEV);
 	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c
index 5c3e1b3a1f..b23258473b 100644
--- a/src/mainboard/samsung/stumpy/smihandler.c
+++ b/src/mainboard/samsung/stumpy/smihandler.c
@@ -26,8 +26,10 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <cpu/intel/model_206ax/model_206ax.h>
 
-/* Include romstage serial for SIO helper functions */
-#include <superio/ite/it8772f/early_serial.c>
+/* FIXME: Include romstage serial for SIO helper functions */
+#include <superio/ite/it8772f/early_init.c>
+//#include <superio/ite/it8772f/it8772f.h>
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
 
 int mainboard_io_trap_handler(int smif)
 {
@@ -64,18 +66,18 @@ void mainboard_smi_sleep(u8 slp_typ)
 	case 3:
 	case 4:
 		/* Blink LED */
-		it8772f_enter_conf();
-		it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+		it8772f_enter_conf(DUMMY_DEV);
+		it8772f_sio_write(DUMMY_DEV, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
 		/* Enable blink pin map */
-		it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
+		it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_PINMAP,
 				  SIO_GPIO_BLINK_GPIO45);
 		/* Enable 4HZ blink */
-		it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
+		it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
 		/* Set GPIO to alternate function */
-		reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
+		reg8 = it8772f_sio_read(DUMMY_DEV, GPIO_REG_ENABLE(3));
 		reg8 &= ~(1 << 5);
-		it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
-		it8772f_exit_conf();
+		it8772f_sio_write(DUMMY_DEV, GPIO_REG_ENABLE(3), reg8);
+		it8772f_exit_conf(DUMMY_DEV);
 		break;
 
 	case 5: