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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-01 16:11:48 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:25:34 +0000
commit0cded1f116ed669b6b2b0c8703863691f9957c65 (patch)
tree83d9280b8d6aa5458cdf91f771c914989425d4c4 /src/mainboard
parent4cba419676de40c76e4979957baf6039da8b8bf5 (diff)
soc/intel/tigerlake: Add SMRR Locking support
The SMRR MSRs can be locked, so that a further write to them will cause a #GP. This patch adds that functionality, but since the MSR is a core-level register, it must only be done once per core; if the SoC has hyperthreading enabled, then attempting to write the SMRR Lock bit on the primary thread will cause a #GP when the secondary (sibling) thread attempts to also write to this MSR. BUG=b:164489598 TEST=Boot into OS, verify using `iotools rdmsr` that all threads have the Lock bit set. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4ae7c7f703bdf090144637d071eb810617d9e309 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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