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authorAlec Ari <neotheuser@ymail.com>2012-04-23 20:24:24 -0500
committerPeter Stuge <peter@stuge.se>2012-04-24 03:58:17 +0200
commit02c204706f1f43dd49e8c9cb5136b6a87117dc72 (patch)
tree8d2efa32a4a7c7e8829fda3cc653ec2768c14d33 /src/mainboard
parent8a527cfb49a15a08baffb7fbd6fdc51dbc28e9df (diff)
Fix whitespace for ma785gm
Fix tabs and whitespace for ma785gm mainboard.c file. Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/923 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/gigabyte/ma785gm/mainboard.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index 97a86f6894..989dfb5f50 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -91,7 +91,7 @@ void set_pcie_reset()
*/
int is_dev3_present(void)
{
- return 0;
+ return 0;
}
/*
@@ -122,16 +122,16 @@ static void set_gpio40_gfx(void)
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* set the gfx to 1x16 lanes */
- printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
- /* when the gpio40 is configured as GPIO, this will enable the output */
- pci_write_config32(sm_dev, 0xf8, 0x4);
- dword = pci_read_config32(sm_dev, 0xfc);
- dword &= ~(1 << 10);
-
- /* When the gpio40 is configured as GPIO, this will represent the output value*/
- /* 1 :enable two x8 , 0 : master slot enable only */
- dword &= ~(1 << 26);
- pci_write_config32(sm_dev, 0xfc, dword);
+ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+ /* when the gpio40 is configured as GPIO, this will enable the output */
+ pci_write_config32(sm_dev, 0xf8, 0x4);
+ dword = pci_read_config32(sm_dev, 0xfc);
+ dword &= ~(1 << 10);
+
+ /* When the gpio40 is configured as GPIO, this will represent the output value*/
+ /* 1 :enable two x8 , 0 : master slot enable only */
+ dword &= ~(1 << 26);
+ pci_write_config32(sm_dev, 0xfc, dword);
}
/*************************************************