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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-10-05 18:45:15 -0600
committerMartin Roth <martinroth@google.com>2018-10-12 15:16:23 +0000
commitd1aa8eba72c640e94ef410bbb0f37c35ee8c9a5c (patch)
tree4d073e4d5119b2c140fe4814a203b60bff91d588 /src/mainboard
parentbba0439d09065a3646a85b37b90fcb83a19297c2 (diff)
amd/stoneyridge: Rename GppClkCntrl fields
Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/mainboard.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index bfd1f2f649..ebdcc935e9 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -146,15 +146,15 @@ static void mainboard_init(void *chip_info)
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
- GPP_CLK2_CLOCK_REQ_MAP_MASK,
- GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
- GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
+ GPP_CLK2_REQ_MAP_MASK,
+ GPP_CLK2_REQ_MAP_CLK_REQ2 <<
+ GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
- GPP_CLK0_CLOCK_REQ_MAP_MASK,
- GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<
- GPP_CLK0_CLOCK_REQ_MAP_SHIFT);
+ GPP_CLK0_REQ_MAP_MASK,
+ GPP_CLK0_REQ_MAP_CLK_REQ0 <<
+ GPP_CLK0_REQ_MAP_SHIFT);
}
/*************************************************