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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-09-10 13:42:00 -0700
committerMartin Roth <martinroth@google.com>2018-09-17 16:27:50 +0000
commitc703beb31d8f95c1e861cb4007b02c3eaaf93c33 (patch)
treec4a7d0b99a6136feed9f08a1ce55340859cf1b28 /src/mainboard
parent1b25f1b47c57e32f2a27480e12daa61331e456a3 (diff)
mb/google/kahlee/variants/baseboard: Set STAPM percentage
Default STAPM percentage causes a lot of thermal throttling on grunt. AMD experimented with 80%, it works for grunt. This is initial code to provide easy change path for other grunt based platforms. BUG=b:111608748 TEST=build and boot grunt. Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c21
-rw-r--r--src/mainboard/google/kahlee/variants/grunt/devicetree.cb3
2 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index 4c5a294c52..74578c27b2 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -17,6 +17,8 @@
#include <amdblocks/agesawrapper.h>
#include <variant/gpio.h>
#include <boardid.h>
+#include <chip.h>
+#include <soc/pci_devs.h>
static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for NC*/
@@ -147,8 +149,27 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
/*---------------------------------------------------------------------------*/
VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
+ const struct soc_amd_stoneyridge_config *cfg;
+ const struct device *dev = dev_find_slot(0, GNB_DEVFN);
+ struct _PLATFORM_CONFIGURATION *platform;
+
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
+ " config, STAPM unchanged\n");
+ return;
+ }
+ cfg = dev->chip_info;
+ platform = &InitEarly->PlatformConfig;
+ if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) {
+ platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
+ platform->PlatStapmConfig.CfgStapmTimeConstant =
+ cfg->stapm_time;
+ platform->PkgPwrLimitDC = cfg->stapm_power;
+ platform->PkgPwrLimitAC = cfg->stapm_power;
+ platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
+ }
}
diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
index b749a9406c..fad9c0d98c 100644
--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
@@ -20,6 +20,9 @@ chip soc/amd/stoneyridge
register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
register "uma_size" = "32 * MiB"
+ register "stapm_percent" = "80"
+ register "stapm_time" = "2500"
+ register "stapm_power" = "7800"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{