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authorBora Guvendik <bora.guvendik@intel.com>2018-12-14 14:13:03 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-29 07:19:42 +0000
commit94bb9a9f5f30ec8893173a72080090d1c04d2a73 (patch)
treec89ae1ea2a9dcdc5a4c97028f268c99aa9ac85f5 /src/mainboard
parentf0a017fe8288e16adbecf8998e99c2cadc3e12de (diff)
mb/google/octopus: Override emmc DLL values for Fleex
New emmc DLL values for Fleex. BUG=b:120561055 TEST=Boot to OS, chromeos-install, mmc_test Change-Id: Id0022e9d0f0a7802113bbf193decff3c8aaa04f8 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/30226 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/octopus/variants/fleex/overridetree.cb41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index bcf771b7f4..a6df66b562 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -1,5 +1,46 @@
chip soc/intel/apollolake
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-16.32.
+ # [14:8] steps of delay for DDR mode, each 125ps.
+ # [6:0] steps of delay for SDR mode, each 125ps.
+ register "emmc_tx_cmd_cntl" = "0x505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-16.33.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0a0c"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-16.34.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x1c282828"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-16.35.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x00181818"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-16.37.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x1001f"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-16.36.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
+ register "emmc_rx_strobe_cntl" = "0x0b0b"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |