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authorRonald G. Minnich <rminnich@gmail.com>2013-03-18 09:49:54 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-03-26 01:42:40 +0100
commit9427ca151e44644238b1b52138894195a9f5175f (patch)
treeefca5b1829cd9f89f27e85f92dd49c7c3087230a /src/mainboard
parentf9be756b559ccc567e5412c85b5ded98f19617e7 (diff)
samsung/exynos5: add resource functions for the display port
This does NOT turn on the graphics. The device tree has been changed enough so that, at the very least, the correct functions are called at the correct time, with the correct paramaters. We decided to yank the I2C entries as they did not obvious function and might not even have been correct. Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. We realized that the display code should be part of the cpu -- that's how the hardware works! Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2615 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/snow/devicetree.cb38
1 files changed, 13 insertions, 25 deletions
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index 5ad786ef55..cfe5cf183d 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -17,30 +17,18 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# FIXME: this is just a stub for now
chip cpu/samsung/exynos5250
-
-device cpu_cluster 0 on
-end
-
-device domain 0 on
- chip drivers/generic/generic # I2C0 controller
- device i2c 6 on end # ?
- device i2c 9 on end # ?
- end
- chip cpu/samsung/exynos5-common/displayport
- register "xres" = "1366"
- register "yres" = "768"
- register "bpp" = "16"
- # complex magic timing!
- register "clkval_f" = "2"
- register "upper_margin" = "14"
- register "lower_margin" = "3"
- register "vsync" = "5"
- register "left_margin" = "80"
- register "right_margin" = "48"
- register "hsync" = "32"
- register "lcdbase" = "0x10000000"
- end
-end
+ device cpu_cluster 0 on end
+ register "xres" = "1366"
+ register "yres" = "768"
+ register "bpp" = "16"
+ # complex magic timing!
+ register "clkval_f" = "2"
+ register "upper_margin" = "14"
+ register "lower_margin" = "3"
+ register "vsync" = "5"
+ register "left_margin" = "80"
+ register "right_margin" = "48"
+ register "hsync" = "32"
+ register "lcdbase" = "0x50000000"
end