diff options
| author | Shelley Chen <shchen@chromium.org> | 2017-06-29 14:58:59 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-14 22:47:31 +0000 |
| commit | 8c81c6ac436c8eac0e312cd2a34133d4a7f5d991 (patch) | |
| tree | 3ee4dd4afce1ececfb6db0902dbdd6f13e5c4c94 /src/mainboard | |
| parent | 20c3ea5c4f2c83df7c9416b2b9cbcff63e2c74f1 (diff) | |
google/fizz: Override PL2 and SysPL2 values
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/fizz/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/fizz/mainboard.c | 28 |
2 files changed, 29 insertions, 1 deletions
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a493de5535..bf9f0c9ef9 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -210,7 +210,7 @@ chip soc/intel/skylake }" register "speed_shift_enable" = "1" - register "tdp_pl2_override" = "7" + register "tdp_psyspl2" = "90" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index a925f084c7..76fb2b8f9b 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -15,8 +15,10 @@ #include <arch/acpi.h> #include <console/console.h> +#include <chip.h> #include <device/device.h> #include <ec/ec.h> +#include <intelblocks/mp_init.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -24,6 +26,28 @@ static const char *oem_id = "GOOGLE"; static const char *oem_table_id = "FIZZ"; +/* + * mainboard_get_pl2 + * + * @return value Pl2 should be set to based on cpu id + * + * TODO: This is purely based on cpu id, which only works for the + * current build because we have a different cpu id per sku. However, + * on the next build, we'll have distinct board ids per sku. We'll + * need to modify that at this point. + */ +static u32 mainboard_get_pl2(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + if (cpuidr.eax == CPUID_KABYLAKE_Y0) { + /* i7 needs higher pl2 */ + return 44; + } + return 29; +} + static void mainboard_init(device_t dev) { mainboard_ec_init(); @@ -58,6 +82,10 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { device_t tpm; + device_t root = SA_DEV_ROOT; + config_t *conf = root->chip_info; + + conf->tdp_pl2_override = mainboard_get_pl2(); dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; |