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authorV Sowmya <v.sowmya@intel.com>2018-12-24 09:34:15 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-12-25 03:43:34 +0000
commit656015c258bc131f5fe3b25af23743c11407b1d0 (patch)
tree1484194d7adb61eee4721c3bbec42d02fd3ce4e6 /src/mainboard
parent6aaae1c89341f6f25b003fa0976cdc0620a75d34 (diff)
mb/google/hatch: Modify hatch SPI flash layout
This patch modifies the hatch flash layout to support IFWI 1.6 with the following regions, Flash Region 0: Descriptor [0x0 - 0xFFF] Flash Region 1: IFWI (consist of ME and PMC FW) [0x1000 - 0x3FFFFF] Flash Region 2: BIOS [0x1400000 - 0x1FFFFFF] Change-Id: I3d05fb50e970737a2552b85d6aebed943bf2b6cb Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30413 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/hatch/chromeos.fmd24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
index 066cfbf62d..53ba33804f 100644
--- a/src/mainboard/google/hatch/chromeos.fmd
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -1,20 +1,20 @@
FLASH@0xfe000000 0x2000000 {
- SI_ALL@0x0 0x300000 {
+ SI_ALL@0x0 0x400000 {
SI_DESC@0x0 0x1000
- SI_ME@0x1000 0x2ff000
+ SI_ME@0x1000 0x3ff000
}
- SI_BIOS@0x1000000 0x1000000 {
- RW_SECTION_A@0x0 0x300000 {
+ SI_BIOS@0x1400000 0xC00000 {
+ RW_SECTION_A@0x0 0x2d0000 {
VBLOCK_A@0x0 0x10000
- FW_MAIN_A(CBFS)@0x10000 0x2effc0
- RW_FWID_A@0x2fffc0 0x40
+ FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+ RW_FWID_A@0x2cffc0 0x40
}
- RW_SECTION_B@0x300000 0x300000 {
+ RW_SECTION_B@0x2d0000 0x2d0000 {
VBLOCK_B@0x0 0x10000
- FW_MAIN_B(CBFS)@0x10000 0x2effc0
- RW_FWID_B@0x2fffc0 0x40
+ FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+ RW_FWID_B@0x2cffc0 0x40
}
- RW_MISC@0x600000 0x30000 {
+ RW_MISC@0x5a0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
@@ -27,8 +27,8 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
- RW_LEGACY(CBFS)@0x630000 0x5a0000
- WP_RO@0xbd0000 0x430000 {
+ RW_LEGACY(CBFS)@0x5d0000 0x200000
+ WP_RO@0x7d0000 0x430000 {
RO_VPD@0x0 0x4000
RO_SECTION@0x4000 0x42c000 {
FMAP@0x0 0x800