mainboard/hp: Add ProBook 6360b

Most of the code is generated using autoport.

Working:
* booting Arch Linux from SeaBIOS
* PCIe/SATA/USB ports (see overridetree and early_init for lists)
* LVDS, DisplayPort, VGA, 3.5 mm jacks, RJ-45
* keyboard, touchpad
* C-States, S3 suspend

Not working:
* rfkill hotkey
* color of the mute hotkey
* sleep f-key

Untested:
* internal speakers and microphone (defective on my machine)
* FireWire
* docking station
* TPM (SeaBIOS detects it, no further test done)

Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Change-Id: I916583fad375f16e5b02388cbcad2e8a993e042f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

9 files changed, 415 insertions, 0 deletions

diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig b/src/mainboard/hp/snb_ivb_laptops/Kconfig
index d4bf19ac23..812c630b13 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Kconfig
+++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig
@@ -29,6 +29,7 @@ config VARIANT_DIR
 	default "8470p"          if BOARD_HP_8470P
 	default "8770w"          if BOARD_HP_8770W
 	default "folio_9470m"    if BOARD_HP_FOLIO_9470M
+	default "probook_6360b"  if BOARD_HP_PROBOOK_6360B
 	default "revolve_810_g1" if BOARD_HP_REVOLVE_810_G1
 
 config MAINBOARD_PART_NUMBER
@@ -40,6 +41,7 @@ config MAINBOARD_PART_NUMBER
 	default "EliteBook 8470p"          if BOARD_HP_8470P
 	default "EliteBook 8770w"          if BOARD_HP_8770W
 	default "EliteBook Folio 9470m"    if BOARD_HP_FOLIO_9470M
+	default "ProBook 6360b"            if BOARD_HP_PROBOOK_6360B
 	default "EliteBook Revolve 810 G1" if BOARD_HP_REVOLVE_810_G1
 
 config OVERRIDE_DEVICETREE
@@ -65,6 +67,7 @@ config USBDEBUG_HCD_INDEX
 	default 2 if BOARD_HP_8470P
 	default 2 if BOARD_HP_8770W
 	default 0 if BOARD_HP_FOLIO_9470M
+	default 1 if BOARD_HP_PROBOOK_6360B # FIXME: check this
 	default 2 if BOARD_HP_REVOLVE_810_G1 # FIXME: check this
 
 endif
diff --git a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name
index 8931cf19e6..8a271909bc 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Kconfig.name
+++ b/src/mainboard/hp/snb_ivb_laptops/Kconfig.name
@@ -79,6 +79,21 @@ config BOARD_HP_FOLIO_9470M
 	select MAINBOARD_USES_IFD_GBE_REGION
 	select SOUTHBRIDGE_INTEL_C216
 
+config BOARD_HP_PROBOOK_6360B
+	bool "ProBook 6360b"
+
+	select BOARD_HP_SNB_IVB_LAPTOPS
+	select BOARD_ROMSIZE_KB_4096
+	select GFX_GMA_PANEL_1_ON_LVDS
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_HAS_LPC_TPM
+	select MAINBOARD_HAS_TPM1
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_SMSC_LPC47N217
+
 config BOARD_HP_REVOLVE_810_G1
 	bool "EliteBook Revolve 810 G1"
 
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt
new file mode 100644
index 0000000000..9f32b2703f
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: https://support.hp.com/us-en/product/hp-probook-6360b-notebook-pc/5045581
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt
new file mode 100644
index 0000000000..14ed640d2a
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/data.vbt
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c
new file mode 100644
index 0000000000..95243016e6
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/early_init.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/smsc/lpc47n217/lpc47n217.h>
+#include <ec/hp/kbc1126/ec.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 }, /* left front */
+	{ 1, 1, 0 }, /* left rear, debug */
+	{ 1, 1, 1 }, /* eSATA */
+	{ 1, 1, 1 }, /* webcam */
+	{ 1, 0, 2 },
+	{ 1, 0, 2 }, /* bluetooth */
+	{ 0, 0, 3 },
+	{ 0, 0, 3 },
+	{ 1, 1, 4 }, /* fingerprint reader */
+	{ 1, 1, 4 }, /* WWAN */
+	{ 1, 0, 5 }, /* right */
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	kbc1126_enter_conf();
+	kbc1126_mailbox_init();
+	kbc1126_kbc_init();
+	kbc1126_ec_init();
+	kbc1126_pm1_init();
+	kbc1126_exit_conf();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads
new file mode 100644
index 0000000000..3df1e37f3e
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gma-mainboard.ads
@@ -0,0 +1,22 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      LVDS,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c
new file mode 100644
index 0000000000..c281dcd5b9
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/gpio.c
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_OUTPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0 = GPIO_LEVEL_LOW,
+	.gpio11 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio3 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio7 = GPIO_INVERT,
+	.gpio10 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_OUTPUT,
+	.gpio37 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_GPIO,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_OUTPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_OUTPUT,
+	.gpio73 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio68 = GPIO_LEVEL_HIGH,
+	.gpio70 = GPIO_LEVEL_HIGH,
+	.gpio71 = GPIO_LEVEL_HIGH,
+	.gpio72 = GPIO_LEVEL_LOW,
+	.gpio73 = GPIO_LEVEL_HIGH,
+	.gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c
new file mode 100644
index 0000000000..40de8bc56b
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d7605,	/* Codec Vendor / Device ID: IDT */
+	0x103c1620,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x103c1620),
+	AZALIA_PIN_CFG(0, 0x0a, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0421401f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x04a11020),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x0f, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x10, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x11, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x40f000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x40f000f0),
+
+	0x11c11040,	/* Codec Vendor / Device ID: LSI */
+	0x103c3066,	/* Subsystem ID */
+	1,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(1, 0x103c3066),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
new file mode 100644
index 0000000000..3289588132
--- /dev/null
+++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	register "gpu_cpu_backlight" = "0x0000014a"
+
+	device domain 0 on
+		subsystemid 0x103c 0x1621 inherit
+
+		device pci 01.0 off end # PEG
+		device pci 02.0 on  end # iGPU
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "gen1_dec" = "0x007c0201"
+			register "gen2_dec" = "0x000c0101"
+			register "gen3_dec" = "0x00fcfe01"
+			register "gen4_dec" = "0x000402e9"
+			register "gpi6_routing" = "2"
+			register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
+			# HDD(0), ODD(1), docking(3, 5), eSATA(4)
+			# FIXME: ports 3, 5 are untested
+			register "sata_port_map" = "0x3b"
+
+			device pci 1c.0 on  end # PCIe Port #1
+			device pci 1c.1 on      # PCIe Port #2, ExpressCard
+				smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort"
+					"ExpressCard Slot" "SlotDataBusWidth1X"
+			end
+			device pci 1c.2 on  end # PCIe Port #3, SD/MMC and FireWire
+			device pci 1c.3 on      # PCIe Port #4, WLAN
+				smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
+					"SlotLengthShort" "Mini PCIe" "SlotDataBusWidth1X"
+			end
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 on  end # PCIe Port #7, WWAN
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1f.0 on
+				chip ec/hp/kbc1126
+					register "ec_data_port" = "0x60"
+					register "ec_cmd_port"  = "0x64"
+					register "ec_ctrl_reg"  = "0xca"
+					register "ec_fan_ctrl_value" = "0x6e"
+					device pnp ff.1 off end
+				end
+				chip superio/smsc/lpc47n217
+					device pnp 4e.3 on      # Parallel
+						io  0x60  = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 4e.4 on      # COM1
+						io  0x60  = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 4e.5 off end # COM2
+				end
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+			end
+		end
+	end
+end