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authordavid <david_wu@quantatw.com>2015-12-04 14:04:15 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-15 12:00:59 +0100
commit228aae589cca0f0025da476150da247c247a711a (patch)
treee7214a0bf64ca1c44234741397132559ff654ea0 /src/mainboard
parent4d27c42604034acd3f7252e46b0c6d3a8510e3ae (diff)
google/lars: Disable kepler device
Disable kepler device, it is removed and was not used on proto anyway. BUG=none BRANCH=none TEST=build and boot on lars proto Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1 Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315950 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12950 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/lars/devicetree.cb9
-rwxr-xr-xsrc/mainboard/google/lars/gpio.h4
2 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index d74392165f..677ee0bcc8 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -43,15 +43,12 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1"
- # Enable Root port 1 and 5.
+ # Enable Root port 1.
register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
- register "PcieRpClkReqSupport[4]" = "1"
- # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+ # RP 1 uses SRCCLKREQ1#
register "PcieRpClkReqNumber[0]" = "1"
- register "PcieRpClkReqNumber[4]" = "2"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_FLEX" # Camera
@@ -106,7 +103,7 @@ chip soc/intel/skylake
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h
index bc11729f74..3aebebc0aa 100755
--- a/src/mainboard/google/lars/gpio.h
+++ b/src/mainboard/google/lars/gpio.h
@@ -115,7 +115,7 @@ static const struct pad_config gpio_table[] = {
/* UART0_RXD */ /* GPP_C8 */
/* UART0_TXD */ /* GPP_C9 */
/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),
-/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP),
+/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
@@ -225,7 +225,7 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
-/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
};
#endif