summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@google.com>2018-12-08 12:00:17 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-10 08:53:57 +0000
commit1a1f00cf413df295186a226150ca82d1f5d7ee23 (patch)
tree4e2a9d8a59a43c360bfb4aa731de7c033fde195c /src/mainboard
parentf63c3f6448ccff7236fa121308a3efb337245e27 (diff)
mb/google/sarien: Setup GPIOs again after FSP-S
Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration if specific UPD variables are not set as it expects. This affects the display-related SOC pads with the following UPD variables: UINT8 DdiPortBHpd; // GPP_E13 UINT8 DdiPortCHpd; // GPP_E14 UINT8 DdiPortDHpd; // GPP_E15 UINT8 DdiPortFHpd; // GPP_E16 UINT8 DdiPortBDdc; // GPP_E18/GPP_E19 UINT8 DdiPortCDdc; // GPP_E20/GPP_E21 UINT8 DdiPortDDdc; // GPP_E22/GPP_E23 UINT8 DdiPortFDdc; // GPP_H16/GPP_H17 Until FSP is fixed to not touch the pad configuration this workaround will reprogram the GPIO settings after FSP-S step so they are correct when the OS attempts to use them. This was found in CoffeLake FSP Gold release: https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg As well as the current top-of-tree for the FSP sources. BUG=b:120686247,chromium:913216 TEST=verify correct GPIO configuration for GPP_E group in the kernel Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/ramstage.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index c65104be8b..c2dc27daee 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -27,8 +27,19 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
gpio_configure_pads(gpio_table, num_gpios);
}
+/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
+static void mainboard_init(struct device *dev)
+{
+ const struct pad_config *gpio_table;
+ size_t num_gpios;
+
+ gpio_table = variant_gpio_table(&num_gpios);
+ gpio_configure_pads(gpio_table, num_gpios);
+}
+
static void mainboard_enable(struct device *dev)
{
+ dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}