diff options
| author | Lubomir Rintel <lkundrak@v3.sk> | 2017-03-18 19:29:28 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-28 15:28:06 +0000 |
| commit | b233916f504cd28be9d4d5710328772ba4b28a5a (patch) | |
| tree | 6d87f8cdcb4c73928002879a8679b4d30922df4d /src/mainboard/winnet/g170/dsdt.asl | |
| parent | 24512dee2be71ab4e203070de48f97a1135a7da1 (diff) | |
mainboard/winnet/g170: Add ACPI support
What is present is APIC and legacy interrupt routing and the soft-off sleep
state. Other sleep states are missing, so are the SuperIO devices.
Boots Linux with and without "noapic" and a Windows XP (installed with
factory BIOS, the installer reportedly requires legacy keyboard).
Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/winnet/g170/dsdt.asl')
| -rw-r--r-- | src/mainboard/winnet/g170/dsdt.asl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/mainboard/winnet/g170/dsdt.asl b/src/mainboard/winnet/g170/dsdt.asl new file mode 100644 index 0000000000..17e6a3e084 --- /dev/null +++ b/src/mainboard/winnet/g170/dsdt.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Lubomir Rintel <lkundrak@v3.sk> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20170227 // OEM revision +) +{ + /* Sleep states */ + Name (\_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package (0x04) { 0x02, 0x02, 0x02, 0x02 }) + + /* Interrupt model */ + Method (_PIC, 1) { + Store (Arg0, \_SB.PCI0.ISAC.APIC) + } + + Scope (\_SB) { + /* PCI bus */ + Device (PCI0) { + #include <northbridge/via/cn700/acpi/hostbridge.asl> + #include <southbridge/via/vt8237r/acpi/lpc.asl> + #include <southbridge/via/vt8237r/acpi/default_irq_route.asl> + } + } +} |