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authorArthur Heymans <arthur@aheymans.xyz>2017-12-25 20:13:28 +0100
committerMartin Roth <martinroth@google.com>2018-05-24 13:03:45 +0000
commitb5170c3e92b3f0cbce292f3414375b1326f4dd12 (patch)
tree8dd7d72aaa67d9727813f70445b667bf526b41a9 /src/mainboard/winnet/Kconfig.name
parentf1287266ab7587672080aed2ddbc272a95fba9a3 (diff)
nb/intel/x4x: Implement write leveling
DDR3 adapted a fly-by topology which allows for better signal integrity but at the same time requires additional calibration. This is done by settings the targeted rank in write leveling mode while disabling output buffer on the other ranks. After that the DQS signal gets sampled over DQ until a transition from high to low is found. Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/winnet/Kconfig.name')
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