diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-21 20:06:10 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-21 20:06:10 +0000 |
commit | 9839cbd53fdcfcee52c406d9f52af924192e618d (patch) | |
tree | a38daaa0b545aaf36a7ad5f5df9dfe73e08d97da /src/mainboard/winent/pl6064/romstage.c | |
parent | cf036d1266d7ec307aac437105b094acbc9681ec (diff) |
* clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/winent/pl6064/romstage.c')
-rw-r--r-- | src/mainboard/winent/pl6064/romstage.c | 39 |
1 files changed, 5 insertions, 34 deletions
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 60f2d21093..aa63ab4062 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -57,46 +57,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "lib/generic_sdram.c" #include "cpu/amd/model_lx/cpureginit.c" #include "cpu/amd/model_lx/syspreinit.c" - -struct msrinit { - u32 msrnum; - msr_t msr; - }; - -static const struct msrinit msr_table[] = -{ - {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. - * Rom Properties: Write Serialize, WriteProtect. - * RomBase: 0xFFFC0 - * SysTop to RomBase Properties: Write Serialize, Cache Disable. - * SysTop: 0x000A0 - * System Memory Properties: (Write Back) */ - {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ - {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */ - {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */ - - /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ - {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF - {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF - {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF - {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF - {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF - {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF -}; - -static void msr_init(void) -{ - int i; - for (i = 0; i < ARRAY_SIZE(msr_table); i++) - wrmsr(msr_table[i].msrnum, msr_table[i].msr); -} +#include "cpu/amd/model_lx/msrinit.c" static void mb_gpio_init(void) { /* Early mainboard specific GPIO setup. */ } -void cache_as_ram_main(void) +void main(unsigned long bist) { post_code(0x01); @@ -118,6 +86,9 @@ void cache_as_ram_main(void) uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(ManualConf); cpuRegInit(); |