AMD boards: Fix romstage main() declaration

Boards incorrectly used intel include file for AMD board.

Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

5 files changed, 5 insertions, 5 deletions

diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index b71fe1cebc..a28bf784a2 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -24,6 +24,7 @@
 #include <lib.h>
 #include <northbridge/via/cn700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "southbridge/via/vt8237r/early_serial.c"
@@ -73,7 +74,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 6878623300..9f2c14e3bf 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -30,6 +30,7 @@
 #include <lib.h>
 #include <northbridge/via/vx800/vx800.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include <string.h>
 /* This file contains the board-special SI value for raminit.c. */
@@ -365,7 +366,6 @@ static void EmbedComInit(void)
 #endif
 
 /* cache_as_ram.inc jumps to here. */
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u16 boot_mode;
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index d40fd6910c..f3f0ec6e9d 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -26,6 +26,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <string.h>
 #include <timestamp.h>
 
@@ -37,7 +38,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
 
 /* cache_as_ram.inc jumps to here. */
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 tolm;
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 17efa3812c..7d12e872d2 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -24,6 +24,7 @@
 #include <lib.h>
 #include <northbridge/via/cn700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include <superio/ite/common/ite.h>
@@ -49,7 +50,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
 };
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index f93b09a5e5..d2af46c5c8 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -23,6 +23,7 @@
 #include <lib.h>
 #include <northbridge/via/cx700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "northbridge/via/cx700/early_smbus.c"
 #include "lib/debug.c"
@@ -76,7 +77,6 @@ static void enable_shadow_ram(const struct mem_controller *ctrl)
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Set statically so it should work with cx700 as well */