soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space

read_resources in common/block/pmc/pmc.c is corrupting the BAR
at offset 0x20.

pch_pmc_read_resources
                      |
                      pci_dev_read_resources
                                            |
                                            pci_get_resource
Within pci_get_resource, the BAR is read and written back. Since read of
ACPI BAR does not return the correct value, the subsequent write
corrupts the BAR. Hence re-programming the BAR. Also, reading PMC
STATUSCOMMAND register does not return bit 0 correctly in
pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled.
Hence making sure IO ACCESS gets enabled by setting dev->command

TEST=Can boot to OS
Without this change coreboot will be stuck at "Disabling ACPI via APMC:"

Change-Id: I27062419d06127951ecbbb641835d06ca39ff435
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions