newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 396 deletions

diff --git a/src/mainboard/via/vt8454c/Config.lb b/src/mainboard/via/vt8454c/Config.lb
deleted file mode 100644
index 6faa33c3b2..0000000000
--- a/src/mainboard/via/vt8454c/Config.lb
+++ /dev/null
@@ -1,163 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_MP_TABLE 
-	object mptable.o 
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object irq_tables.o 
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object acpi_tables.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-##
-## Romcc output
-##
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
-	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-mainboardinit cpu/via/car/cache_as_ram.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/cx700
-	device apic_cluster 0 on
-		chip cpu/via/model_c7
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		device pci 0.0 on end # AGP Bridge
-		device pci 0.1 on end # Error Reporting
-		device pci 0.2 on end # Host Bus Control
-		device pci 0.3 on end # Memory Controller
-		device pci 0.4 on end # Power Management
-		device pci 0.7 on end # V-Link Controller
-		device pci 1.0 on     # PCI Bridge
-			device pci 0.0 on end # Onboard Video
-		end # PCI Bridge
-		device pci f.0 on end # IDE/SATA
-		#device pci f.1 on end # IDE
-		device pci 10.0 on end # USB 1.1
-		device pci 10.1 on end # USB 1.1
-		device pci 10.2 on end # USB 1.1
-		device pci 10.4 on end # USB 2.0
-		device pci 11.0 on      # Southbridge LPC
-			chip superio/via/vt1211
-				device pnp 2e.0 on	# Floppy
-					io 0x60 = 0x3f0
-					irq 0x70 = 6
-					drq 0x74 = 2
-				end
-				device pnp 2e.1 on	# Parallel Port
-					io 0x60 = 0x378
-					irq 0x70 = 7
-					drq 0x74 = 3
-				end
-				device pnp 2e.2 on	# COM1
-					io 0x60 = 0x3f8
-					irq 0x70 = 4
-				end
-				device pnp 2e.3 on	# COM2
-					io 0x60 = 0x2f8
-					irq 0x70 = 3
-				end
-				device pnp 2e.b on	# HWM
-					io 0x60 = 0xec00
-				end
-			end # superio
-		end # pci 11.0
-		# 1-4 non existant
-		#device pci 11.5 on end # AC97 Audio
-		#device pci 11.6 off end # AC97 Modem
-		#device pci 12.0 on end  # Ethernet
-	end # pci domain 0
-end # cx700
-
diff --git a/src/mainboard/via/vt8454c/Options.lb b/src/mainboard/via/vt8454c/Options.lb
deleted file mode 100644
index cb796caf97..0000000000
--- a/src/mainboard/via/vt8454c/Options.lb
+++ /dev/null
@@ -1,233 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-## MA 02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_HAVE_LOW_TABLES
-
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-
-uses CONFIG_COMPRESS
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-
-# compiler specifics
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-# Console specifics
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_SMP
-uses CONFIG_IOAPIC
-
-uses CONFIG_GDB_STUB
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xffef0000
-#default CONFIG_DCACHE_RAM_BASE=0xffbf0000
-#default CONFIG_DCACHE_RAM_BASE=0xfec00000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-###
-### Leave this to 0; VGA is handled by seperate code.
-###
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_CONSOLE_VGA=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Use TSC for udelay.
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=15
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to load acpi tables
-##
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Build code to fill in tables both in low and high memory
-##
-default CONFIG_HAVE_LOW_TABLES=1
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_SMP=1
-default CONFIG_IOAPIC=1
-
-###
-### LinuxBIOS layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-## Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
-end
-