Remove all VIA CN700 boards

Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I06840476ad187cbb6e6af554b5c8e8c4d66f6624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

8 files changed, 0 insertions, 380 deletions

diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig
deleted file mode 100644
index d5e1133a64..0000000000
--- a/src/mainboard/via/pc2500e/Kconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-if BOARD_VIA_PC2500E
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_VIA_C7
-	select NORTHBRIDGE_VIA_CN700
-	select SOUTHBRIDGE_VIA_VT8237R
-	select SUPERIO_ITE_IT8716F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select SMP
-	select BOARD_ROMSIZE_KB_512
-
-config MAINBOARD_DIR
-	string
-	default via/pc2500e
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "pc2500e"
-
-config IRQ_SLOT_COUNT
-	int
-	default 10
-
-config VGA_BIOS_FILE
-	string
-	default "M14CRT.ROM"
-
-config VGA_BIOS_ID
-	string
-	default "1106,3344"
-
-endif # BOARD_VIA_PC2500E
diff --git a/src/mainboard/via/pc2500e/Kconfig.name b/src/mainboard/via/pc2500e/Kconfig.name
deleted file mode 100644
index 0de65a7e7e..0000000000
--- a/src/mainboard/via/pc2500e/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_VIA_PC2500E
-	bool "pc2500e"
diff --git a/src/mainboard/via/pc2500e/board_info.txt b/src/mainboard/via/pc2500e/board_info.txt
deleted file mode 100644
index 8b98abf4d2..0000000000
--- a/src/mainboard/via/pc2500e/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: mini
-Board URL: http://www.idot.com.tw/en/products/mb-pc2500e/
-ROM package: PLCC
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/via/pc2500e/cmos.layout b/src/mainboard/via/pc2500e/cmos.layout
deleted file mode 100644
index 6d8fd5b05a..0000000000
--- a/src/mainboard/via/pc2500e/cmos.layout
+++ /dev/null
@@ -1,43 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-entries
-
-#start-bit length  config config-ID   name
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-456          1       e       1        ECC_memory
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb
deleted file mode 100644
index 17bc35efc9..0000000000
--- a/src/mainboard/via/pc2500e/devicetree.cb
+++ /dev/null
@@ -1,89 +0,0 @@
-chip northbridge/via/cn700			# Northbridge
-  device domain 0 on			# PCI domain
-    subsystemid 0x1019 0xaa51 inherit
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      device pci f.0 on end			# SATA
-      device pci f.1 on end			# IDE
-      register "fn_ctrl_lo" = "0x80"
-      register "fn_ctrl_hi" = "0x1d"
-      device pci 10.0 on end			# UHCI
-      device pci 10.1 on end			# UHCI
-      device pci 10.2 on end			# UHCI
-      device pci 10.3 on end			# UHCI
-      device pci 10.4 on end			# EHCI
-      device pci 10.5 on end			# UDCI
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/ite/it8716f		# Super I/O
-          device pnp 2e.0 on			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.2 off			# COM2 (N/A on this board)
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.3 on			# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.4 on			# Environment controller
-            io 0x60 = 0x290
-            io 0x62 = 0x0000
-            irq 0x70 = 9
-          end
-          device pnp 2e.5 off			# PS/2 keyboard (not used)
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.6 off			# PS/2 mouse (not used)
-            irq 0x70 = 12
-          end
-          device pnp 2e.7 on			# GPIO
-            io 0x60 = 0x0000
-            io 0x62 = 0x0800
-            io 0x64 = 0x0000
-          end
-          device pnp 2e.8 off			# MIDI port (N/A)
-            io 0x60 = 0x300
-            irq 0x70 = 10
-          end
-          device pnp 2e.9 off			# Game port (N/A)
-            io 0x60 = 0x201
-          end
-          device pnp 2e.a on			# Consumer IR
-            io 0x60 = 0x310
-            irq 0x70 = 11
-          end
-        end
-      end
-      device pci 11.5 on end			# AC'97 audio
-      # device pci 11.6 off end			# AC'97 modem (N/A)
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-  device cpu_cluster 0 on			# APIC cluster
-    chip cpu/via/c7			# VIA C7
-      device lapic 0 on end			# APIC
-    end
-  end
-end
diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c
deleted file mode 100644
index e514df4363..0000000000
--- a/src/mainboard/via/pc2500e/irq_tables.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,
-	PIRQ_VERSION,
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x11 << 3) | 0x0,	/* Interrupt router device */
-	0x828,			/* IRQs devoted exclusively to PCI usage */
-	0x1106,			/* Vendor */
-	0x596,			/* Device */
-	0,			/* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x3e,			/* Checksum */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
-		{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
-		{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
-		{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
-		{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
-		{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
-		{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
deleted file mode 100644
index 9b92b002cf..0000000000
--- a/src/mainboard/via/pc2500e/mptable.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int isa_bus;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &isa_bus);
-
-/* I/O APICs:	APIC ID	Version	State		Address*/
-	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
-
-	/* Now, assemble the table. */
-	mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
-
-#define PCI_INT(bus, dev, fn, pin) \
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
-		bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin))
-
-	// PCI slot 1
-	PCI_INT(0, 8, 0, 16);
-	PCI_INT(0, 8, 1, 17);
-	PCI_INT(0, 8, 2, 18);
-	PCI_INT(0, 8, 3, 19);
-
-	// PCI slot 2
-	PCI_INT(0, 9, 0, 17);
-	PCI_INT(0, 9, 1, 18);
-	PCI_INT(0, 9, 2, 19);
-	PCI_INT(0, 9, 3, 16);
-
-	// SATA
-	PCI_INT(0, 15, 1, 20);
-
-	// USB
-	PCI_INT(0, 16, 0, 21);
-	PCI_INT(0, 16, 1, 21);
-	PCI_INT(0, 16, 2, 21);
-	PCI_INT(0, 16, 3, 21);
-
-	// Audio
-	PCI_INT(0, 17, 2, 22);
-
-	// Ethernet
-	PCI_INT(0, 18, 0, 23);
-
-	/* Onboard VGA */
-	PCI_INT(1, 0, 0, 16);
-
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	mptable_lintsrc(mc, 0);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
deleted file mode 100644
index d0ecae361d..0000000000
--- a/src/mainboard/via/pc2500e/romstage.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <lib.h>
-#include <northbridge/via/cn700/raminit.h>
-#include <cpu/x86/bist.h>
-#include <delay.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8716f/it8716f.h>
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-
-int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-static const struct mem_controller ctrl = {
-	.d0f0 = 0x0000,
-	.d0f2 = 0x2000,
-	.d0f3 = 0x3000,
-	.d0f4 = 0x4000,
-	.d0f7 = 0x7000,
-	.d1f0 = 0x8000,
-	.channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
-};
-
-void main(unsigned long bist)
-{
-	/* Enable multifunction for northbridge. */
-	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
-
-	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	enable_smbus();
-	smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
-	report_bist_failure(bist);
-	ddr_ram_setup(&ctrl);
-}