Ron,

Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>

Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 197 insertions, 0 deletions

diff --git a/src/mainboard/via/epia-n/Config.lb b/src/mainboard/via/epia-n/Config.lb
new file mode 100644
index 0000000000..d524c88281
--- /dev/null
+++ b/src/mainboard/via/epia-n/Config.lb
@@ -0,0 +1,197 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 VIA Technologies, Inc.
+## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+
+include /config/nofailovercalculation.lb
+
+##
+## Set all of the defaults for an x86 architecture
+##
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+
+#object vgabios.o
+
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+
+if CONFIG_HAVE_ACPI_TABLES
+#acpi_create_fadt is located in VT8237R code
+	object dsdt.o
+	object acpi_tables.o
+end
+makerule ./failover.E
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of coreboot startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/via/cn400			# Northbridge
+
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/via/model_c3			# VIA C3
+      device apic 0 on end			# APIC
+    end
+  end
+
+  device pci_domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      device pci f.0 on end			# IDE/SATA
+	  device pci f.1 on end			# IDE
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci 10.0 on end			# OHCI
+      device pci 10.1 on end			# OHCI
+      device pci 10.2 on end			# OHCI
+      device pci 10.3 on end			# OHCI
+      device pci 10.4 on end			# EHCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/winbond/w83697hf		# Super I/O
+          device pnp 2e.0 off			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 off			# Parallel Port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 off			# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 off			# IR Port
+            io 0x60 = 0x000
+          end
+          device pnp 2e.7 off			# GPIO 1
+            io 0x60 = 0x201			# 0x201
+          end
+          device pnp 2e.8 off			# GPIO 5
+            io 0x60 = 0x330			# 0x330
+          end
+          device pnp 2e.9 off			# GPIO 2, 3,and 4
+            io 0x60 = 0x000			#
+          end
+          device pnp 2e.a off			# ACPI
+            io 0x60 = 0x000			#
+          end
+          device pnp 2e.b on			# HWM
+            io 0x60 = 0x290
+			irq 0x70 = 0
+          end
+        end
+      end
+      device pci 11.5 off end			# AC'97 audio
+      # device pci 11.6 off end			# AC'97 Modem
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+end