First bunch of coding style and consistency cleanups for the

EPIA-M700 target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 49 insertions, 50 deletions

diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb
index 2c5b80bb3b..70f669ef62 100644
--- a/src/mainboard/via/epia-m700/Config.lb
+++ b/src/mainboard/via/epia-m700/Config.lb
@@ -28,19 +28,19 @@ driver wakeup.o
 if HAVE_PIRQ_TABLE object irq_tables.o end
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-#	object ssdt.o
-	object acpi_tables.o
+  object fadt.o
+  object dsdt.o
+  # object ssdt.o
+  object acpi_tables.o
 end
-# these lines maybe noused
+# These lines maybe noused.
 makerule ./failover.E
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+  depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+  action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 makerule ./failover.inc
-	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
-	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+  depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+  action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
 end
 if USE_DCACHE_RAM
   if CONFIG_USE_INIT
@@ -60,22 +60,23 @@ end
 mainboardinit cpu/via/16bit/entry16.inc
 ldscript /cpu/via/16bit/entry16.lds
 
-mainboardinit northbridge/via/vx800/romstrap.inc  
+mainboardinit northbridge/via/vx800/romstrap.inc
 ldscript /northbridge/via/vx800/romstrap.lds
 
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/32bit/entry32.lds
 if USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
+  mainboardinit cpu/x86/16bit/reset16.inc
+  ldscript /cpu/x86/16bit/reset16.lds
 else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
+  mainboardinit cpu/x86/32bit/reset32.inc
+  ldscript /cpu/x86/32bit/reset32.lds
 end
 
-#mainboardinit arch/i386/lib/cpu_reset.inc    
-#here cpu_reset.inc have label _cpu_reset, which is needed in failover,c, but cpu_reset.inc also has code to jump to __main() which is not included in cache_as_ram_auto_auto.c 
-
+# mainboardinit arch/i386/lib/cpu_reset.inc
+# Here cpu_reset.inc have label _cpu_reset, which is needed in failover.c,
+# but cpu_reset.inc also has code to jump to __main() which is not included
+# in cache_as_ram_auto_auto.c.
 
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
@@ -85,13 +86,13 @@ if USE_DCACHE_RAM
 end
 
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-# failover.inc need defination in cpu_reset.inc, but we do not include cpu_reset.inc,so ...
-#  mainboardinit ./failover.inc  
+  ldscript /arch/i386/lib/failover.lds
+  # failover.inc need definition in cpu_reset.inc, but we do not include
+  # cpu_reset.inc,so ...
+  # mainboardinit ./failover.inc
 end
-#mainboardinit cpu/x86/fpu/enable_fpu.inc
-#mainboardinit cpu/x86/mmx/enable_mmx.inc
-
+# mainboardinit cpu/x86/fpu/enable_fpu.inc
+# mainboardinit cpu/x86/mmx/enable_mmx.inc
 
 if USE_DCACHE_RAM
   if CONFIG_USE_INIT
@@ -100,35 +101,33 @@ if USE_DCACHE_RAM
     mainboardinit ./cache_as_ram_auto.inc
   end
 end
- 
-#mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+# mainboardinit cpu/x86/mmx/disable_mmx.inc
 dir /pc80
 
 config chip.h
 
-
 chip northbridge/via/vx800	# Northbridge
-	device pci_domain 0 on
-		device pci 0.0 on end # AGP Bridge
-		device pci 0.1 on end # Error Reporting
-		device pci 0.2 on end # Host Bus Control		
-		device pci 0.3 on end # Memory Controller
-		device pci 0.4 on end # Power Management
-		device pci 0.7 on end # V-Link Controller
-		device pci 1.0 on end # PCI Bridge
-			#device pci f.0 on end # IDE/SATA
-			#device pci f.1 on end # IDE
-			#device pci 10.0 on end # USB 1.1
-			#device pci 10.1 on end # USB 1.1
-			#device pci 10.2 on end # USB 1.1
-			#device pci 10.4 on end # USB 2.0
-			#device pci 11.0 on      # Southbridge LPC
-			#end # pci 11.0		
-			
-	end # pci domain 0
-	device apic_cluster 0 on		# APIC cluster
-		chip cpu/via/model_c7			# VIA C7
-			device apic 0 on end		# APIC
-		end
-	end	
-end # vx800
+  device pci_domain 0 on
+    device pci 0.0 on end	# AGP Bridge
+    device pci 0.1 on end	# Error Reporting
+    device pci 0.2 on end	# Host Bus Control
+    device pci 0.3 on end	# Memory Controller
+    device pci 0.4 on end	# Power Management
+    device pci 0.7 on end	# V-Link Controller
+    device pci 1.0 on end	# PCI Bridge
+    # device pci f.0 on end	# IDE/SATA
+    # device pci f.1 on end	# IDE
+    # device pci 10.0 on end	# USB 1.1
+    # device pci 10.1 on end	# USB 1.1
+    # device pci 10.2 on end	# USB 1.1
+    # device pci 10.4 on end	# USB 2.0
+    # device pci 11.0 on	# Southbridge LPC
+    # end
+  end
+  device apic_cluster 0 on	# APIC cluster
+    chip cpu/via/model_c7	# VIA C7
+      device apic 0 on end	# APIC
+    end
+  end
+end