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authorBari Ari <bari@onelabs.com>2008-09-01 01:48:07 +0000
committerPeter Stuge <peter@stuge.se>2008-09-01 01:48:07 +0000
commitd4759d0f22892cc740d5aae559eaf5b9b5ab735a (patch)
treeadbd541327d47654590814029eb3493d2e5deef3 /src/mainboard/via/epia-cn/Config.lb
parent3153863567f51c9173227b9cb4375d53e6f3e6ed (diff)
This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy. Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/epia-cn/Config.lb')
-rw-r--r--src/mainboard/via/epia-cn/Config.lb14
1 files changed, 8 insertions, 6 deletions
diff --git a/src/mainboard/via/epia-cn/Config.lb b/src/mainboard/via/epia-cn/Config.lb
index 52eb18492f..6e48b2b6de 100644
--- a/src/mainboard/via/epia-cn/Config.lb
+++ b/src/mainboard/via/epia-cn/Config.lb
@@ -98,12 +98,14 @@ chip northbridge/via/cn700 # Northbridge
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
device pci f.0 on end # IDE
- register "fn_ctrl_lo" = "0x8a"
- register "fn_ctrl_hi" = "0x9d"
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.3 on end # USB 1.1
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
chip superio/via/vt1211 # Super I/O
device pnp 2e.0 off # Floppy