summaryrefslogtreecommitdiff
path: root/src/mainboard/up
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2023-02-01 08:02:23 +0100
committerLean Sheng Tan <sheng.tan@9elements.com>2023-02-03 19:55:53 +0000
commit64e2ecb36fd1d7b289cd9671dcfae2e335528d81 (patch)
treea48c10aa42b234c85e8afaf28d0f11231e275e28 /src/mainboard/up
parenta10a86d2bc8d3daf9394ccb0c7e0479ad1eec6e5 (diff)
soc/intel/apl: Move cpu cluster to chipset.cb
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/mainboard/up')
-rw-r--r--src/mainboard/up/squared/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb
index 867f3a5180..4b0d5f79b1 100644
--- a/src/mainboard/up/squared/devicetree.cb
+++ b/src/mainboard/up/squared/devicetree.cb
@@ -20,7 +20,6 @@ chip soc/intel/apollolake
# 0:HS400 (Default) 1:HS200 2:DDR50
register "emmc_host_max_speed" = "1"
- device cpu_cluster 0 on end
device domain 0 on
subsystemid 0x8086 0x7270 inherit
device pci 00.0 on end # - Host Bridge