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authorJonathan Zhang <jonzhang@fb.com>2020-08-04 12:59:24 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:05:49 +0000
commit9366885a424b8135c8a52a7e8c209c8a28ffebcf (patch)
tree13e081c80d3532d8ab659062a4b0c4e02c642d4f /src/mainboard/up
parent7f4395f40e8d7255a11f26841e7651e4a3e3cb22 (diff)
soc/intel/xeon_sp/cpx: display FSP_PREV_BOOT_ERR_SRC_HOB
Before MRC code execution, FSP interrogates EMCA MSR registers and other registers to see if there are fatal errors happened during previous boot session. If there are, error records are saved into FSP_PREV_BOOT_ERR_SRC_HOB. When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means the HOB does not contain any valid error record. TESTED=Injects MCE error through cscript, reboot into OS, check boot log: 0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION 5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID ================ PREV_BOOT_ERR_SRC HOB DATA ================ hob: 0x75904d88, Length: 0x42 MCBANK ERR INFO: Segment: 0, Socket: 0, ApicId: 0x0 McBankNum: 0x3 McBankStatus: 0xfe00000000800400 McBankAddr: 0xf0ff McBankMisc: 0xfffffff0 MCBANK ERR INFO: Segment: 0, Socket: 0, ApicId: 0x0 McBankNum: 0x4 McBankStatus: 0xfe00000000800400 McBankAddr: 0xfff0 McBankMisc: 0xfffffff0 0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00 B............... 0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00 ................ 0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00 ................ 0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00 ................ 0x75904dc8: 00 00 Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/up')
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