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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2020-03-11 16:16:16 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:41:37 +0000
commit91dddd47b3e5a34124e34222ab3f2a1f00ce9246 (patch)
tree3ff01ea023a54ec138520373656a3d16c0991354 /src/mainboard/up
parentfc932374a2860addbdf00dc3bd141b556508b8f3 (diff)
tgl boards: Configure retimer Aux orientation
In order to create a working baseline all ports are being set to have retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not misconfigure the ports. Volteer will need some additional changes after this is implemented to account for ports that do not have a retimer. This setting is in the process of being documented in the TGL EDS and we can update once it is fully understood what this setting is changing on the SOC side. BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on Volteer, Connecting Type-c display should work regardless of Type-c cable orientation. Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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