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authorJonathan Zhang <jonzhang@fb.com>2020-04-02 17:27:54 -0700
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2020-06-04 15:42:10 +0000
commit7919d618f8ffd742df1e5d4804656b20412f4999 (patch)
tree7cdb6c95a1401efc5354e85a3e16d3b22a7747c4 /src/mainboard/up/squared
parentbd3245c2075c4915b2256593b414c8355d31001a (diff)
soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration
Add PCIe enumeration and resource assignment/allocation. Xeon-SP processor family has split IIO design, where PCIe domain 0 is split into multiple stacks. Each stack has its own resource ranges (eg. IO resource, mem32 resource, mem64 resource). The stack itself is not PCIe device, it does not have config space to be probed/programmed. The stack is programmed by FSP. coreboot needs to take into account of stack when doing PCIe enumeration and resource allocation. Current coreboot PCIe resource allocator does not support the concept of split IIO stack, thus entire support is done locally in this patch. In near future, improvements will be done, first generalize for xeon-sp, then generalize for coreboot PCIe device code. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com> Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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