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author | Patrick Rudolph <siro@das-labor.org> | 2017-05-03 18:38:21 +0200 |
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committer | Patrick Rudolph <siro@das-labor.org> | 2017-05-21 16:38:20 +0200 |
commit | 7565cf1a49bf9688e636e1ebc6a4cb8e1e567e1b (patch) | |
tree | bf8543e00c5979ff62739ffe1dc903c775b780c4 /src/mainboard/tyan | |
parent | cfa2eaa4cc268e9ed23c5a8635bb8125d985c94e (diff) |
sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"
Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/tyan')
0 files changed, 0 insertions, 0 deletions