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authorArne Georg Gleditsch <arne.gleditsch@numascale.com>2008-10-30 20:17:11 +0000
committerMarc Jones <marc.jones@amd.com>2008-10-30 20:17:11 +0000
commit429d6b66928119df0ba0c69d7f1232e8c2b904da (patch)
tree5f78d974f4a155bcc95373ffdd8d7f0f09ad4b8c /src/mainboard/tyan
parentedc7ef2b76f8d49d1eeae9a111bdcae3f288d6f9 (diff)
Here's a patch towards r3690 upping the ROM size for the S2912 Fam10 target to 1M.
Both regular and abuild images have been boot tested successfully. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2912_fam10/Config.lb6
-rw-r--r--src/mainboard/tyan/s2912_fam10/Options.lb6
2 files changed, 5 insertions, 7 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/Config.lb b/src/mainboard/tyan/s2912_fam10/Config.lb
index 5af4ffba48..e82f4bee88 100644
--- a/src/mainboard/tyan/s2912_fam10/Config.lb
+++ b/src/mainboard/tyan/s2912_fam10/Config.lb
@@ -92,7 +92,7 @@ if USE_DCACHE_RAM
else
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
@@ -105,7 +105,7 @@ else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
@@ -345,7 +345,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 6.0 on
chip drivers/pci/onboard
device pci 4.0 on end
- register "rom_address" = "0xfff80000"
+ register "rom_address" = "0xfff00000"
end
end # PCI
device pci 6.1 off end # AZA
diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb
index 5e048a0ce2..a0dacf676b 100644
--- a/src/mainboard/tyan/s2912_fam10/Options.lb
+++ b/src/mainboard/tyan/s2912_fam10/Options.lb
@@ -126,7 +126,7 @@ uses AMD_UCODE_PATCH_FILE
##
## ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=524288
+default ROM_SIZE=1024*1024
#default ROM_SIZE=0x100000
##
@@ -135,9 +135,7 @@ default ROM_SIZE=524288
#default FALLBACK_SIZE=131072
#default FALLBACK_SIZE=0x40000
-#FALLBACK: ROM_SIZE-4K
-default FALLBACK_SIZE=ROM_SIZE-0x01000
-#FAILOVER: 4K
+default FALLBACK_SIZE=0x3f000
default FAILOVER_SIZE=0x01000
#more 1M for pgtbl