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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-01-06 09:14:08 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-01-06 09:14:08 +0000
commit753169dc251e3f5e71a9f678c93b68c040aebbf0 (patch)
treeceeb73865d95baead8572ac423ed633f2d5c5495 /src/mainboard/tyan
parent95c50c6091cdc700c79da832f61b2a94b3e5c87c (diff)
Kconfig builds all boards now.
This patch also aligns the configuration of a couple of boards more closely to what newconfig does. Also, the romstrap inc/lds files are declared in the Makefiles of the southbridges they belong to, instead of some global file. AMD CPUs have their own timer functions, so disable UDELAY_IO for them and set HAVE_INIT_TIMER as appropriate, same for emulation/qemu-x86. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2912_fam10/Kconfig42
-rw-r--r--src/mainboard/tyan/s2912_fam10/Makefile.inc9
2 files changed, 34 insertions, 17 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index 2363a2131f..f2dff1ff76 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -13,10 +13,10 @@ config BOARD_TYAN_S2912_FAM10
select HAVE_HARD_RESET
select IOAPIC
select LIFT_BSP_APIC_ID
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select BOARD_ROMSIZE_KB_1024
select ENABLE_APIC_EXT_ID
select AMDMCT
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
@@ -25,22 +25,22 @@ config MAINBOARD_DIR
config DCACHE_RAM_BASE
hex
- default 0xc8000
+ default 0xc4000
depends on BOARD_TYAN_S2912_FAM10
config DCACHE_RAM_SIZE
hex
- default 0x08000
+ default 0x0c000
depends on BOARD_TYAN_S2912_FAM10
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
- default 0x01000
+ default 0x04000
depends on BOARD_TYAN_S2912_FAM10
config APIC_ID_OFFSET
hex
- default 16
+ default 0
depends on BOARD_TYAN_S2912_FAM10
config MEM_TRAIN_SEQ
@@ -95,12 +95,12 @@ config HW_MEM_HOLE_SIZEK
config MAX_CPUS
int
- default 2
+ default 8
depends on BOARD_TYAN_S2912_FAM10
config MAX_PHYSICAL_CPUS
int
- default 1
+ default 2
depends on BOARD_TYAN_S2912_FAM10
config HW_MEM_HOLE_SIZE_AUTO_INC
@@ -110,12 +110,12 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
config HT_CHAIN_UNITID_BASE
hex
- default 0x0
+ default 0x1
depends on BOARD_TYAN_S2912_FAM10
config HT_CHAIN_END_UNITID_BASE
hex
- default 0x0
+ default 0x20
depends on BOARD_TYAN_S2912_FAM10
config USE_INIT
@@ -148,3 +148,27 @@ config AMD_UCODE_PATCH_FILE
default "mc_patch_01000095.h"
depends on BOARD_TYAN_S2912_FAM10
+config SERIAL_CPU_INIT
+ bool
+ default n
+ depends on BOARD_TYAN_S2912_FAM10
+
+config ACPI_SSDTX_NUM
+ hex
+ default 0x1f
+ depends on BOARD_TYAN_S2912_FAM10
+
+config RAMBASE
+ hex
+ default 0x200000
+ depends on BOARD_TYAN_S2912_FAM10
+
+config RAMTOP
+ hex
+ default 0x1000000
+ depends on BOARD_TYAN_S2912_FAM10
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+ depends on BOARD_TYAN_S2912_FAM10
diff --git a/src/mainboard/tyan/s2912_fam10/Makefile.inc b/src/mainboard/tyan/s2912_fam10/Makefile.inc
index c21cdb3574..de14fd8a1e 100644
--- a/src/mainboard/tyan/s2912_fam10/Makefile.inc
+++ b/src/mainboard/tyan/s2912_fam10/Makefile.inc
@@ -30,19 +30,12 @@ obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o
-crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
-crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
-crt0-y += ../../../../src/arch/i386/lib/id.inc
-crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
-ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
-ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
-ldscript-y += ../../../../src/arch/i386/lib/id.lds
-ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb