Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51

Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 578 insertions, 50 deletions

diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb
index 67ee157f6e..95ef0464fe 100644
--- a/src/mainboard/tyan/s4882/Config.lb
+++ b/src/mainboard/tyan/s4882/Config.lb
@@ -16,6 +16,7 @@ end
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_STREAM     = 1
 
 ##
 ## Compute where this copy of linuxBIOS will start in the boot rom
@@ -34,6 +35,7 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
 
 arch i386 end 
 
+
 ##
 ## Build the objects we have code for in this directory.
 ##
@@ -42,39 +44,61 @@ driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
+if USE_DCACHE_RAM
 
-##
-## Romcc output
-##
-makerule ./failover.E
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+	if CONFIG_USE_INIT
 
-makerule ./failover.inc
-        depends "$(MAINBOARD)/failover.c ./romcc"
-        action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+		makerule ./auto.o
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+	        	action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+		end
 
-makerule ./auto.E
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-        depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+	else
 
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-mainboardinit arch/i386/lib/jmp_auto_out.inc
+		makerule ./auto.inc
+        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+		        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+        		action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+		        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+			end
+	end
+else
+
+	##
+	## Romcc output
+	##
+	makerule ./failover.E
+        	depends "$(MAINBOARD)/failover.c ./romcc"
+	        action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	end
+
+	makerule ./failover.inc
+	        depends "$(MAINBOARD)/failover.c ./romcc"
+        	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+	end
+
+	makerule ./auto.E
+        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	        action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	end
+
+	makerule ./auto.inc
+        	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	        action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+	end
+
+	##
+	## Setup RAM
+	##
+	mainboardinit cpu/x86/fpu/enable_fpu.inc
+	mainboardinit cpu/x86/mmx/enable_mmx.inc
+	mainboardinit cpu/x86/sse/enable_sse.inc
+	mainboardinit ./auto.inc
+	mainboardinit cpu/x86/sse/disable_sse.inc
+	mainboardinit cpu/x86/mmx/disable_mmx.inc
+	mainboardinit arch/i386/lib/jmp_auto_out.inc
+
+end
 
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
@@ -82,7 +106,16 @@ mainboardinit arch/i386/lib/jmp_auto_out.inc
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
 ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript /cpu/amd/car/cache_as_ram.lds
+        end
+end
+
 
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
@@ -95,8 +128,11 @@ else
 	ldscript /cpu/x86/32bit/reset32.lds 
 end
 
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
+if USE_DCACHE_RAM
+else
+	### Should this be in the northbridge code?
+	mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -104,27 +140,51 @@ mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+
+if USE_DCACHE_RAM
+	##
+	## Setup Cache-As-Ram
+	##
+	mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
+	if USE_DCACHE_RAM
+		ldscript /arch/i386/lib/failover.lds
+	else
+       		ldscript /arch/i386/lib/failover.lds
+	        mainboardinit ./failover.inc
+	end
 end
 
-###
-### O.k. We aren't just an intermediary anymore!
-###
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+	if CONFIG_USE_INIT
+		initobject auto.o
+	else
+		mainboardinit ./auto.inc
+	end
 
-mainboardinit arch/i386/lib/jmp_auto.inc
+else
+
+	# ROMCC
+	mainboardinit arch/i386/lib/jmp_auto.inc
+
+end
 
 ##
 ## Include the secondary Configuration files 
 ##
 if CONFIG_CHIP_NAME
-        config chip.h
+	config chip.h
 end
 
 # sample config for tyan/s4882
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb
index e1a431bde3..56a2548228 100644
--- a/src/mainboard/tyan/s4882/Options.lb
+++ b/src/mainboard/tyan/s4882/Options.lb
@@ -11,7 +11,6 @@ uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
 uses CONFIG_MAX_PHYSICAL_CPUS
 uses CONFIG_LOGICAL_CPUS
-uses SERIAL_CPU_INIT
 uses CONFIG_IOAPIC
 uses CONFIG_SMP
 uses FALLBACK_SIZE
@@ -48,16 +47,21 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 uses CONFIG_CONSOLE_SERIAL8250
 uses HAVE_INIT_TIMER
 uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
 uses OBJCOPY
 uses CONFIG_CHIP_NAME
-uses CONFIG_CONSOLE_BTEXT
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses K8_E0_MEM_HOLE_SIZEK
 
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+
 ###
 ### Build options
 ###
@@ -85,7 +89,7 @@ default HAVE_HARD_RESET=1
 ##
 ## Funky hard reset implementation
 ## 
-default HARD_RESET_BUS=1
+default HARD_RESET_BUS=3
 default HARD_RESET_DEVICE=4
 default HARD_RESET_FUNCTION=0
 
@@ -122,18 +126,25 @@ default CONFIG_MAX_CPUS=8
 default CONFIG_MAX_PHYSICAL_CPUS=4
 default CONFIG_LOGICAL_CPUS=1
 
-#default SERIAL_CPU_INIT=0
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
 
 #1G memory hole
 default K8_E0_MEM_HOLE_SIZEK=0x100000
 
-#BTEXT Console
-#default CONFIG_CONSOLE_BTEXT=1
-
 #VGA Console
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=1
+
 ##
 ## Build code to setup a generic IOAPIC
 ##
@@ -142,8 +153,8 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="Tyan"
-default MAINBOARD_VENDOR="s4882"
+default MAINBOARD_PART_NUMBER="s4882"
+default MAINBOARD_VENDOR="Tyan"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
 
@@ -232,9 +243,9 @@ default TTYS0_LCS=0x3
 ## SPEW       9   Way too many details             
 
 ## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=7
+default  DEFAULT_CONSOLE_LOGLEVEL=8
 ## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=7
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
 
 ##
 ## Select power on after power fail setting
diff --git a/src/mainboard/tyan/s4882/cache_as_ram_auto.c b/src/mainboard/tyan/s4882/cache_as_ram_auto.c
new file mode 100644
index 0000000000..4e1b8483fc
--- /dev/null
+++ b/src/mainboard/tyan/s4882/cache_as_ram_auto.c
@@ -0,0 +1,457 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+ 
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+#include "northbridge/amd/amdk8/cpu_rev.c"
+#define K8_HT_FREQ_1G_SUPPORT 0
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static void hard_reset(void)
+{
+        set_bios_reset();
+
+        /* enable cf9 */
+        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+        /* reset */
+        outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+
+static void memreset_setup(void)
+{
+   if (is_cpu_pre_c0()) {
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
+   }
+   else {
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
+   }
+        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+   if (is_cpu_pre_c0()) {
+        udelay(800);
+        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+        udelay(90);
+   }
+}
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+#define SMBUS_HUB 0x18
+        int ret,i;
+        unsigned device=(ctrl->channel0[0])>>8;
+        i=2;
+        do {
+                ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+        } while ((ret!=0) && (i-->0));
+
+        smbus_write_byte(SMBUS_HUB, 0x03, 0);
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#define K8_4RANK_DIMM_SUPPORT 1
+
+#include "northbridge/amd/amdk8/raminit.c"
+#if 0
+        #define ENABLE_APIC_EXT_ID 1
+        #define APIC_ID_OFFSET 0x10
+        #define LIFT_BSP_APIC_ID 0
+#else 
+        #define ENABLE_APIC_EXT_ID 0
+#endif
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+ /* tyan does not want the default */
+#include "resourcemap.c" 
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#include "cpu/amd/dualcore/dualcore.c"
+#endif
+#define FIRST_CPU  1
+#define SECOND_CPU 1
+
+#define THIRD_CPU  1 
+#define FOURTH_CPU 1 
+
+#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
+
+#define RC0 ((1<<2)<<8)
+#define RC1 ((1<<1)<<8)
+#define RC2 ((1<<4)<<8)
+#define RC3 ((1<<3)<<8)
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void real_main(unsigned long bist);
+
+void amd64_main(unsigned long bist)
+{
+#if CONFIG_LOGICAL_CPUS==1
+        struct node_core_id id;
+#else
+        unsigned nodeid;
+#endif
+        /* Make cerain my local apic is useable */
+//        enable_lapic();
+
+#if CONFIG_LOGICAL_CPUS==1
+        id = get_node_core_id_x();
+        /* Is this a cpu only reset? */
+        if (cpu_init_detected(id.nodeid)) {
+#else
+//        nodeid = lapicid();
+	nodeid = get_node_id();
+        /* Is this a cpu only reset? */
+        if (cpu_init_detected(nodeid)) {
+#endif
+                if (last_boot_normal()) {
+                        goto normal_image;
+                } else {
+                        goto cpu_reset;
+                }
+        }
+
+        /* Is this a secondary cpu? */
+        if (!boot_cpu()) {
+                if (last_boot_normal()) {
+                        goto normal_image;
+                } else {
+                        goto fallback_image;
+                }
+        }
+
+        /* Nothing special needs to be done to find bus 0 */
+        /* Allow the HT devices to be found */
+
+        enumerate_ht_chain();
+
+        /* Setup the ck804 */
+        amd8111_enable_rom();
+
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal()) {
+                goto normal_image;
+        }
+        /* This is the primary cpu how should I boot? */
+        else if (do_normal_boot()) {
+                goto normal_image;
+        }
+        else {
+                goto fallback_image;
+        }
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist) /* inputs */
+                );
+ cpu_reset:
+#if 0
+        //CPU reset will reset memtroller ???
+        asm volatile ("jmp __cpu_reset" 
+                : /* outputs */ 
+                : "a"(bist) /* inputs */
+                );
+#endif
+
+ fallback_image:
+        real_main(bist);
+}
+void real_main(unsigned long bist)
+#else
+void amd64_main(unsigned long bist)
+#endif
+{
+	static const struct mem_controller cpu[] = {
+#if FIRST_CPU
+                {
+                        .node_id = 0,
+                        .f0 = PCI_DEV(0, 0x18, 0),
+                        .f1 = PCI_DEV(0, 0x18, 1),
+                        .f2 = PCI_DEV(0, 0x18, 2),
+                        .f3 = PCI_DEV(0, 0x18, 3),
+                        .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
+                        .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
+                },
+#endif
+#if SECOND_CPU
+                {
+                        .node_id = 1,
+                        .f0 = PCI_DEV(0, 0x19, 0),
+                        .f1 = PCI_DEV(0, 0x19, 1),
+                        .f2 = PCI_DEV(0, 0x19, 2),
+                        .f3 = PCI_DEV(0, 0x19, 3),
+                        .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
+                        .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
+
+                },
+#endif
+
+#if THIRD_CPU
+                {
+                        .node_id = 2,
+                        .f0 = PCI_DEV(0, 0x1a, 0),
+                        .f1 = PCI_DEV(0, 0x1a, 1),
+                        .f2 = PCI_DEV(0, 0x1a, 2),
+                        .f3 = PCI_DEV(0, 0x1a, 3),
+                        .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
+                        .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
+
+                },
+#endif
+#if FOURTH_CPU
+                {
+                        .node_id = 3,
+                        .f0 = PCI_DEV(0, 0x1b, 0),
+                        .f1 = PCI_DEV(0, 0x1b, 1),
+                        .f2 = PCI_DEV(0, 0x1b, 2),
+                        .f3 = PCI_DEV(0, 0x1b, 3),
+                        .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
+                        .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
+
+                },
+#endif
+	};
+
+        int needs_reset;
+	unsigned cpu_reset = 0;
+
+        if (bist == 0) {
+#if CONFIG_LOGICAL_CPUS==1
+        	struct node_core_id id;
+#else
+	        unsigned nodeid;
+#endif
+                /* Skip this if there was a built in self test failure */
+//                amd_early_mtrr_init(); # don't need, already done in cache_as_ram
+
+#if CONFIG_LOGICAL_CPUS==1
+                set_apicid_cpuid_lo();
+		id = get_node_core_id_x(); // that is initid
+        #if ENABLE_APIC_EXT_ID == 1
+                if(id.coreid == 0) {
+                        enable_apic_ext_id(id.nodeid);
+                }
+        #endif
+#else
+                nodeid = get_node_id();
+        #if ENABLE_APIC_EXT_ID == 1
+                enable_apic_ext_id(nodeid);
+        #endif
+#endif
+
+                enable_lapic();
+                init_timer();
+
+
+#if CONFIG_LOGICAL_CPUS==1
+        #if ENABLE_APIC_EXT_ID == 1
+            #if LIFT_BSP_APIC_ID == 0
+                if( id.nodeid != 0 ) //all except cores in node0
+            #endif
+                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
+        #endif
+                if(id.coreid == 0) {
+                        if (cpu_init_detected(id.nodeid)) {
+				cpu_reset = 1;
+				goto cpu_reset_x;
+                        }
+                        distinguish_cpu_resets(id.nodeid);
+                }
+#else
+        #if ENABLE_APIC_EXT_ID == 1
+            #if LIFT_BSP_APIC_ID == 0
+                if(nodeid != 0)
+            #endif
+                        lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
+
+        #endif
+                if (cpu_init_detected(nodeid)) {
+			cpu_reset = 1;
+			goto cpu_reset_x;
+                }
+                distinguish_cpu_resets(nodeid);
+#endif
+
+
+                if (!boot_cpu()
+#if CONFIG_LOGICAL_CPUS==1 
+                        || (id.coreid != 0)
+#endif
+                ) {
+			// We need stop the CACHE as RAM for this CPU too
+			#include "cpu/amd/car/cache_as_ram_post.c"
+                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
+                }
+        }
+
+	
+ 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+
+	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+        setup_s4882_resource_map();
+#if 0
+        dump_pci_device(PCI_DEV(0, 0x18, 0));
+	dump_pci_device(PCI_DEV(0, 0x19, 0));
+#endif
+
+	needs_reset = setup_coherent_ht_domain();
+	
+#if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
+        start_other_cores();
+#endif
+        needs_reset |= ht_setup_chains_x();
+
+       	if (needs_reset) {
+               	print_info("ht reset -\r\n");
+               	soft_reset();
+       	}
+
+	enable_smbus();
+
+	memreset_setup();
+	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+#if 1
+        {
+        /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+        unsigned v_esp;
+        __asm__ volatile (
+                "movl   %%esp, %0\n\t"
+                : "=a" (v_esp)
+        );
+#if CONFIG_USE_INIT
+        printk_debug("v_esp=%08x\r\n", v_esp);
+#else           
+        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
+#endif    
+        }
+#endif
+
+
+
+cpu_reset_x:
+
+#if CONFIG_USE_INIT
+        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
+#else
+        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
+#endif
+
+	if(cpu_reset == 0) {
+	        print_debug("Clearing initial memory region: ");
+	}
+	print_debug("No cache as ram now - ");
+
+	/* store cpu_reset to ebx */
+        __asm__ volatile (
+                "movl %0, %%ebx\n\t"
+                ::"a" (cpu_reset)
+        );
+
+	if(cpu_reset==0) {
+#define CLEAR_FIRST_1M_RAM 1
+#include "cpu/amd/car/cache_as_ram_post.c"
+	}
+	else {
+#undef CLEAR_FIRST_1M_RAM 
+#include "cpu/amd/car/cache_as_ram_post.c"
+	}
+
+	__asm__ volatile (
+                /* set new esp */ /* before _RAMBASE */
+                "movl   %0, %%ebp\n\t"
+                "movl   %0, %%esp\n\t"
+                ::"a"( _RAMBASE - 4 )
+	);
+
+	{
+		unsigned new_cpu_reset;
+
+		/* get back cpu_reset from ebx */
+		__asm__ volatile (
+			"movl %%ebx, %0\n\t"
+			:"=a" (new_cpu_reset)
+		);
+
+		print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
+		if(new_cpu_reset==0) {        
+		        print_debug("done\r\n");	
+		} else 
+		{	
+			print_debug("\r\n");
+		}
+
+#if CONFIG_USE_INIT
+                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+#else
+                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
+#endif
+		/*copy and execute linuxbios_ram */
+		copy_and_run(new_cpu_reset);
+		/* We will not return */
+	}
+
+
+	print_debug("should not be here -\r\n");
+
+}