Merging patches from Yinghai Lu (fb2_s4882_changes.diff.bz2):

- new motherboard: Tyan s4882
- minor changes to 2880, s2881, s2885, s4880


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 245 insertions, 0 deletions

diff --git a/src/mainboard/tyan/s4882/Config.lb b/src/mainboard/tyan/s4882/Config.lb
new file mode 100644
index 0000000000..ea826238b5
--- /dev/null
+++ b/src/mainboard/tyan/s4882/Config.lb
@@ -0,0 +1,245 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses ARCH
+uses HARD_RESET_BUS
+uses HARD_RESET_DEVICE
+uses HARD_RESET_FUNCTION
+
+#
+#
+###
+### Set all of the defaults for an x86 architecture
+###
+#
+#
+###
+### Build the objects we have code for in this directory.
+###
+##object mainboard.o
+config chip.h
+register "fixup_scsi" = "1" 
+#register "fixup_vga" = "1"
+
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+driver mainboard.o
+driver lsi_scsi.o
+#driver adaptec_scsi.o
+driver si_sata.o
+#driver intel_nic.o
+#object reset.o
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#
+default HARD_RESET_BUS=1
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
+#
+arch i386 end
+#cpu k8 end
+#
+###
+### Build our 16 bit and 32 bit linuxBIOS entry code
+###
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+mainboardinit cpu/i386/bist32.inc
+ldscript /cpu/i386/entry16.lds
+ldscript /cpu/i386/entry32.lds
+#
+###
+### Build our reset vector (This is where linuxBIOS is entered)
+###
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/i386/reset16.inc 
+	ldscript /cpu/i386/reset16.lds 
+else
+	mainboardinit cpu/i386/reset32.inc 
+	ldscript /cpu/i386/reset32.lds 
+end
+#
+#### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+#
+###
+### Include an id string (For safe flashing)
+###
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+#
+####
+#### This is the early phase of linuxBIOS startup 
+#### Things are delicate and we test to see if we should
+#### failover to another image.
+####
+#option MAX_REBOOT_CNT=2
+if USE_FALLBACK_IMAGE
+  ldscript /arch/i386/lib/failover.lds 
+end
+#
+###
+### Setup our mtrrs
+###
+mainboardinit cpu/k8/earlymtrr.inc
+###
+### Only the bootstrap cpu makes it here.
+### Failover if we need to 
+###
+#
+if USE_FALLBACK_IMAGE
+  mainboardinit ./failover.inc
+end
+
+#
+#
+###
+### Setup the serial port
+###
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
+mainboardinit cpu/i386/bist32_fail.inc
+#
+####
+#### O.k. We aren't just an intermediary anymore!
+####
+#
+###
+### Romcc output
+###
+#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
+#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
+#mainboardinit .failover.inc
+
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c" 
+	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
+
+makerule ./failover.inc
+	depends "./romcc ./failover.E"
+	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+
+makerule ./auto.E 
+        depends "$(MAINBOARD)/auto.c option_table.h"
+        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc 
+	depends "./romcc ./auto.E"
+	action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
+#	action	"./romcc -mcpu=k8  -O ./auto.E > auto.inc"
+end
+mainboardinit cpu/k8/enable_mmx_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/k8/disable_mmx_sse.inc
+#
+###
+### Include the secondary Configuration files 
+###
+northbridge amd/amdk8 "mc0"
+        pci 0:18.0
+        pci 0:18.0
+        pci 0:18.0
+        pci 0:18.1
+        pci 0:18.2
+        pci 0:18.3
+        southbridge amd/amd8131 "amd8131" link 1
+                pci 0:0.0
+                pci 0:0.1
+                pci 0:1.0
+                pci 0:1.1
+	end
+        southbridge amd/amd8111 "amd8111" link 1
+                pci 0:0.0
+                pci 0:1.0 on
+                pci 0:1.1 on
+                pci 0:1.2 on
+                pci 0:1.3 on
+                pci 0:1.5 off
+                pci 0:1.6 off
+                pci 1:0.0 on
+                pci 1:0.1 on
+                pci 1:0.2 on
+                pci 1:1.0 off
+                superio winbond/w83627hf link 1
+                        pnp 2e.0 off #  Floppy
+                                 io 0x60 = 0x3f0
+                                irq 0x70 = 6
+                                drq 0x74 = 2
+                        pnp 2e.1 off #  Parallel Port
+                                 io 0x60 = 0x378
+                                irq 0x70 = 7
+                        pnp 2e.2 on #  Com1
+                                 io 0x60 = 0x3f8
+                                irq 0x70 = 4
+                        pnp 2e.3 off #  Com2
+                                 io 0x60 = 0x2f8
+                                irq 0x70 = 3
+                        pnp 2e.5 on #  Keyboard
+                                 io 0x60 = 0x60
+                                 io 0x62 = 0x64
+                                irq 0x70 = 1
+                        pnp 2e.6 off #  CIR
+                        pnp 2e.7 off #  GAME_MIDI_GIPO1
+                        pnp 2e.8 off #  GPIO2
+                        pnp 2e.9 off #  GPIO3
+                        pnp 2e.a off #  ACPI
+                        pnp 2e.b off #  HW Monitor
+                end
+        end
+end
+
+northbridge amd/amdk8 "mc1"
+        pci 0:19.0
+        pci 0:19.0
+        pci 0:19.0
+        pci 0:19.1
+        pci 0:19.2
+        pci 0:19.3
+end
+
+northbridge amd/amdk8 "mc2"
+        pci 0:1a.0
+        pci 0:1a.0
+        pci 0:1a.0
+        pci 0:1a.1
+        pci 0:1a.2
+        pci 0:1a.3
+end
+
+
+northbridge amd/amdk8 "mc3"
+        pci 0:1b.0
+        pci 0:1b.0
+        pci 0:1b.0
+        pci 0:1b.1
+        pci 0:1b.2
+        pci 0:1b.3
+end
+
+
+dir /pc80
+#dir /bioscall
+
+cpu k8 "cpu0"
+  register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
+end
+
+cpu k8 "cpu1"
+end
+
+cpu k8 "cpu2"
+end
+
+cpu k8 "cpu3"
+end