fixes for tyan

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 165 insertions, 92 deletions

diff --git a/src/mainboard/tyan/s4880/Config.lb b/src/mainboard/tyan/s4880/Config.lb
index ccc4784935..58e71b4668 100644
--- a/src/mainboard/tyan/s4880/Config.lb
+++ b/src/mainboard/tyan/s4880/Config.lb
@@ -1,6 +1,9 @@
 uses HAVE_MP_TABLE
 uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
 #
@@ -19,10 +22,17 @@ register "fixup_scsi" = "1"
 #register "fixup_vga" = "1"
 
 
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
 driver mainboard.o
-driver lsi_scsi.o
+#driver lsi_scsi.o
 #driver adaptec_scsi.o
-driver si_sata.o
+#driver si_sata.o
 #driver intel_nic.o
 object reset.o
 if HAVE_MP_TABLE object mptable.o end
@@ -36,6 +46,7 @@ arch i386 end
 ###
 mainboardinit cpu/i386/entry16.inc
 mainboardinit cpu/i386/entry32.inc
+mainboardinit cpu/i386/bist32.inc
 ldscript /cpu/i386/entry16.lds
 ldscript /cpu/i386/entry32.lds
 #
@@ -87,23 +98,15 @@ end
 ###
 ### Setup the serial port
 ###
-#mainboardinit superiowinbond/w83627hf/setup_serial.inc
 mainboardinit pc80/serial.inc
 mainboardinit arch/i386/lib/console.inc
+mainboardinit cpu/i386/bist32_fail.inc
 #
 ####
 #### O.k. We aren't just an intermediary anymore!
 ####
 #
 ###
-### When debugging disable the watchdog timer
-###
-##option MAXIMUM_CONSOLE_LOGLEVEL=7
-#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#
-#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
-#
-###
 ### Romcc output
 ###
 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
@@ -120,8 +123,8 @@ makerule ./failover.inc
 	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 
 makerule ./auto.E 
-	depends	"$(MAINBOARD)/auto.c" 
-	action	"$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+        depends "$(MAINBOARD)/auto.c option_table.h"
+        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 end
 makerule ./auto.inc 
 	depends "./romcc ./auto.E"
@@ -160,6 +163,31 @@ northbridge amd/amdk8 "mc0"
                 pci 1:0.1 on
                 pci 1:0.2 on
                 pci 1:1.0 off
+                superio winbond/w83627hf link 1
+                        pnp 2e.0 off #  Floppy
+                                 io 0x60 = 0x3f0
+                                irq 0x70 = 6
+                                drq 0x74 = 2
+                        pnp 2e.1 off #  Parallel Port
+                                 io 0x60 = 0x378
+                                irq 0x70 = 7
+                        pnp 2e.2 on #  Com1
+                                 io 0x60 = 0x3f8
+                                irq 0x70 = 4
+                        pnp 2e.3 off #  Com2
+                                 io 0x60 = 0x2f8
+                                irq 0x70 = 3
+                        pnp 2e.5 on #  Keyboard
+                                 io 0x60 = 0x60
+                                 io 0x62 = 0x64
+                                irq 0x70 = 1
+                        pnp 2e.6 off #  CIR
+                        pnp 2e.7 off #  GAME_MIDI_GIPO1
+                        pnp 2e.8 off #  GPIO2
+                        pnp 2e.9 off #  GPIO3
+                        pnp 2e.a off #  ACPI
+                        pnp 2e.b off #  HW Monitor
+                end
         end
 end
 
@@ -192,21 +220,9 @@ northbridge amd/amdk8 "mc3"
 end
 
 
-#northbridge amd/amdk8
-#end
-#southbridge amd/amd8111 "amd8111"
-#end
-#southbridge amd/amd8131 "amd8131"
-#end
-#mainboardinit archi386/smp/secondary.inc
-#superio NSC/pc87360
-#	register "com1" = "{1}"
-#	register "lpt" = "{1}"
-#end
 dir /pc80
-##dir /src/superio/winbond/w83627hf
 #dir /bioscall
-#dir /cpu/k8
+
 cpu k8 "cpu0"
   register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 end
diff --git a/src/mainboard/tyan/s4880/auto.c b/src/mainboard/tyan/s4880/auto.c
index f4d898599d..11e6a8b669 100644
--- a/src/mainboard/tyan/s4880/auto.c
+++ b/src/mainboard/tyan/s4880/auto.c
@@ -1,13 +1,16 @@
 #define ASSEMBLY 1
 #include <stdint.h>
 #include <device/pci_def.h>
-#include <cpu/p6/apic.h>
 #include <arch/io.h>
+#include <device/pnp_def.h>
 #include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/k8/apic_timer.c"
@@ -16,6 +19,25 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static void hard_reset(void)
+{
+        set_bios_reset();
+
+        /* enable cf9 */
+        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+        /* reset */
+        outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
 
 
 #define REV_B_RESET 0
@@ -102,8 +124,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 /* include mainboard specific ht code */
 #include "hypertransport.c"
 
-//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -111,38 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "resourcemap.c" /* tyan does not want the default */
 
-static void enable_lapic(void)
-{
-	msr_t msr;
-	msr = rdmsr(0x1b);
-	msr.hi &= 0xffffff00;
-	msr.lo &= 0x000007ff;
-	msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
-	wrmsr(0x1b, msr);
-}
-
-static void stop_this_cpu(void)
-{
-	unsigned apicid;
-	apicid = apic_read(APIC_ID) >> 24;
-
-	/* Send an APIC INIT to myself */
-	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-	apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
-	/* Wait for the ipi send to finish */
-	apic_wait_icr_idle();
-
-	/* Deassert the APIC INIT */
-	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
-	apic_write(APIC_ICR,  APIC_INT_LEVELTRIG | APIC_DM_INIT);
-	/* Wait for the ipi send to finish */
-	apic_wait_icr_idle();
-
-	/* If I haven't halted spin forever */
-	for(;;) {
-		hlt();
-	}
-}
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 
@@ -214,21 +202,26 @@ static void main(void)
 #endif
 	};
 	int i;
-	if (cpu_init_detected()) {
-		asm("jmp __cpu_reset");
-	}
-	enable_lapic();
-	init_timer();
-	if (!boot_cpu() ) {
-//		notify_bsp_ap_is_stopped();
-		stop_this_cpu();
-	}
-	uart_init();
-	console_init();
-	setup_s4880_resource_map();
-	setup_coherent_ht_domain();
-	enumerate_ht_chain(0);
-	distinguish_cpu_resets(0);
+        int needs_reset;
+        enable_lapic();
+        init_timer();
+        if (cpu_init_detected()) {
+                asm("jmp __cpu_reset");
+        }
+        distinguish_cpu_resets();
+        if (!boot_cpu()) {
+                stop_this_cpu();
+        }
+        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+        uart_init();
+        console_init();
+        setup_s4880_resource_map();
+        needs_reset = setup_coherent_ht_domain();
+        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+        if (needs_reset) {
+                print_info("ht reset -");
+                soft_reset();
+        }
 	
 #if 0
 	dump_pci_devices();
diff --git a/src/mainboard/tyan/s4880/cmos.layout b/src/mainboard/tyan/s4880/cmos.layout
index 5ba4c032c1..247715e6ac 100644
--- a/src/mainboard/tyan/s4880/cmos.layout
+++ b/src/mainboard/tyan/s4880/cmos.layout
@@ -29,6 +29,9 @@ entries
 386          1       e       1        ECC_memory
 388          4       r       0        reboot_bits
 392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
 400          1       e       1        power_on_after_fail
 412          4       e       6        debug_level
 416          4       e       7        boot_first
@@ -36,7 +39,14 @@ entries
 424          4       e       7        boot_third
 428          4       h       0        boot_index
 432	     8       h       0        boot_countdown
-1008         16      h       0        check_sum
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
 
 enumerations
 
@@ -66,9 +76,21 @@ enumerations
 7     9     Fallback_HDD
 7     10    Fallback_Floppy
 #7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
 
 checksums
 
-checksum 392 1007 1008
+checksum 392 983 984
 
 
diff --git a/src/mainboard/tyan/s4880/failover.c b/src/mainboard/tyan/s4880/failover.c
index 8eeeaef7e1..b22abfea06 100644
--- a/src/mainboard/tyan/s4880/failover.c
+++ b/src/mainboard/tyan/s4880/failover.c
@@ -3,36 +3,78 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
-#include "arch/romcc_io.h"
+#include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "cpu/p6/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
+#define HAVE_REGPARM_SUPPORT 0
+#if HAVE_REGPARM_SUPPORT
+static unsigned long main(unsigned long bist)
+{
+#else
 static void main(void)
 {
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-	enumerate_ht_chain(0);
+	unsigned long bist = 0;
+#endif
+	/* Make cerain my local apic is useable */
+	enable_lapic();
 
-	/* Setup the 8111 */
-	amd8111_enable_rom();
-
-	/* Is this a cpu reset? */
+	/* Is this a cpu only reset? */
 	if (cpu_init_detected()) {
 		if (last_boot_normal()) {
-			asm("jmp __normal_image");
+			goto normal_image;
 		} else {
-			asm("jmp __cpu_reset");
+			goto cpu_reset;
 		}
 	}
 	/* Is this a secondary cpu? */
-	else if (!boot_cpu() && last_boot_normal()) {
-		asm("jmp __normal_image");
+	if (!boot_cpu()) {
+		if (last_boot_normal()) {
+			goto normal_image;
+		} else {
+			goto fallback_image;
+		}
+	}
+	
+
+	/* Nothing special needs to be done to find bus 0 */
+	/* Allow the HT devices to be found */
+	enumerate_ht_chain();
+	
+	/* Setup the 8111 */
+	amd8111_enable_rom();
+
+	/* Is this a deliberate reset by the bios */
+	if (bios_reset_detected() && last_boot_normal()) {
+		goto normal_image;
 	}
 	/* This is the primary cpu how should I boot? */
 	else if (do_normal_boot()) {
-		asm("jmp __normal_image");
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
 	}
+ normal_image:
+	asm("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+#if HAVE_REGPARM_SUPPORT
+	return bist;
+#else
+	return;
+#endif
 }