diff options
| author | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2005-07-08 02:49:49 +0000 |
| commit | 13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch) | |
| tree | 27cad5581f1fa150f573149d48e82f70ba1b1d9f /src/mainboard/tyan/s4880/cache_as_ram_auto.c | |
| parent | 14cde9e96a777f9d75016a13b23fab0480515f58 (diff) | |
eric patch
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s4880/cache_as_ram_auto.c')
| -rw-r--r-- | src/mainboard/tyan/s4880/cache_as_ram_auto.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/tyan/s4880/cache_as_ram_auto.c b/src/mainboard/tyan/s4880/cache_as_ram_auto.c index f39ff15b4d..bddcd08820 100644 --- a/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ b/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -325,6 +325,7 @@ void amd64_main(unsigned long bist) enable_lapic(); init_timer(); +// post_code(0x30); #if CONFIG_LOGICAL_CPUS==1 #if ENABLE_APIC_EXT_ID == 1 @@ -355,7 +356,6 @@ void amd64_main(unsigned long bist) distinguish_cpu_resets(nodeid); #endif - if (!boot_cpu() #if CONFIG_LOGICAL_CPUS==1 || (id.coreid != 0) @@ -380,9 +380,9 @@ void amd64_main(unsigned long bist) needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); if (needs_reset) { |