diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-18 20:58:41 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-18 20:58:41 +0000 |
| commit | 78acf932912669eb0eb7f7280da1b3c550035ebb (patch) | |
| tree | 89f13a87df362395527d41f42d0a57a167eab8db /src/mainboard/tyan/s2912_fam10 | |
| parent | 2bd91003413d431f0a4db6c3c6691f4b688cf5c5 (diff) | |
Remove remaining uses of
HAVE_FAILOVER_BOOT
HAVE_FALLBACK_BOOT
USE_FAILOVER_IMAGE
USE_FALLBACK_IMAGE
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2912_fam10')
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/Kconfig | 30 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/romstage.c | 10 |
2 files changed, 0 insertions, 40 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 740932ff77..e1ac2dc222 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -38,26 +38,6 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE default 0x04000 depends on BOARD_TYAN_S2912_FAM10 -config USE_FALLBACK_IMAGE - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - -config HAVE_FALLBACK_BOOT - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - -config CONFIG_USE_FAILOVER_IMAGE - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - -config CONFIG_HAVE_FAILOVER_BOOT - bool - default y - depends on BOARD_TYAN_S2912_FAM10 - config APIC_ID_OFFSET hex default 0 @@ -98,16 +78,6 @@ config PCI_64BIT_PREF_MEM default n depends on BOARD_TYAN_S2912_FAM10 -config HAVE_FALLBACK_BOOT - bool - default n - depends on BOARD_TYAN_S2912_FAM10 - -config USE_FALLBACK_IMAGE - bool - default n - depends on BOARD_TYAN_S2912_FAM10 - config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index e8bca07ce5..29e4060243 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -53,7 +53,6 @@ static void post_code(u8 value) { outb(value, 0x80); } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "pc80/serial.c" #include "arch/i386/lib/console.c" #if CONFIG_USBDEBUG_DIRECT @@ -68,15 +67,11 @@ static void post_code(u8 value) { #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" -#if CONFIG_USE_FAILOVER_IMAGE==0 - #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" @@ -142,8 +137,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_10xxx/fidvid.c" -#endif - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -168,7 +161,6 @@ static void sio_setup(void) } -#if CONFIG_USE_FAILOVER_IMAGE==0 #include "spd_addr.h" #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" @@ -317,5 +309,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x43); // Should never see this post code. } - -#endif |