diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-10-08 07:43:09 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-10-08 07:43:09 +0000 |
commit | 5726f92027c4299a7cad46c9153dbe55543efb5e (patch) | |
tree | 3b48da7bf4d3c522769628e36e0b5df329188164 /src/mainboard/tyan/s2912_fam10/Kconfig | |
parent | b97ee05dc72c52fbb694326863b4977736d0f225 (diff) |
Kconfig: AMD Fam10, all Tyan boards.
Fam10 doesn't build due to size constraints at this time.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2912_fam10/Kconfig')
-rw-r--r-- | src/mainboard/tyan/s2912_fam10/Kconfig | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig new file mode 100644 index 0000000000..9b1eb2a7fa --- /dev/null +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -0,0 +1,162 @@ + +config BOARD_TYAN_S2912_FAM10 + bool "S2912_FAM10" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F_1207 + select NORTHBRIDGE_AMD_AMDFAM10 + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + +config MAINBOARD_DIR + string + default tyan/s2912_fam10 + depends on BOARD_TYAN_S2912_FAM10 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_TYAN_S2912_FAM10 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_TYAN_S2912_FAM10 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_TYAN_S2912_FAM10 + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_TYAN_S2912_FAM10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_TYAN_S2912_FAM10 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2912_FAM10 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2912_FAM10 + +config MAINBOARD_PART_NUMBER + string + default "S2912 (Fam10)" + depends on BOARD_TYAN_S2912_FAM10 + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2912_FAM10 + +config MAX_CPUS + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_TYAN_S2912_FAM10 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_TYAN_S2912_FAM10 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_TYAN_S2912_FAM10 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x10f1 + depends on BOARD_TYAN_S2912_FAM10 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2912 + depends on BOARD_TYAN_S2912_FAM10 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_TYAN_S2912_FAM10 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + depends on BOARD_TYAN_S2912_FAM10 + +config ENABLE_APIC_EXT_ID + bool + default y + depends on BOARD_TYAN_S2912_FAM10 + +config AMDMCT + bool + default y + depends on BOARD_TYAN_S2912_FAM10 |