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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2016-08-23 11:20:20 +0530
committerAaron Durbin <adurbin@chromium.org>2016-09-14 22:18:42 +0200
commit35240ebe3c543e3ea416765d980ba8774d14754d (patch)
tree8277ec33ce901dfb4fd5ae9541b9c3e8f88cf459 /src/mainboard/tyan/s2912/Kconfig
parent8cdeef1c0d1e6453a027642d2504e58ab9ac7152 (diff)
soc/intel/apollolake: Update PL1 value in RAPL MMIO register
Due to an incorrect value set for the power limit PL1, the system is not able to leverage full TDP capacity. FSP code sets the PL1 value as 6W in RAPL MMIO register based on fused soc tdp value. This RAPL MMIO register is a physically separate instance from RAPL MSR register. This patch sets PL1 value to 15W in RAPL MMIO register. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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