Whitespace fixes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 158 insertions, 158 deletions

diff --git a/src/mainboard/tyan/s2912/Config.lb b/src/mainboard/tyan/s2912/Config.lb
index 01b7375c80..1075d4264b 100644
--- a/src/mainboard/tyan/s2912/Config.lb
+++ b/src/mainboard/tyan/s2912/Config.lb
@@ -1,23 +1,23 @@
-## 
+##
 ## This file is part of the coreboot project.
-## 
+##
 ## Copyright (C) 2007 AMD
 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## 
+##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
 ## the Free Software Foundation; either version 2 of the License, or
 ## (at your option) any later version.
-## 
+##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
-## 
+##
 ## You should have received a copy of the GNU General Public License
 ## along with this program; if not, write to the Free Software
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
+##
 
 ##
 ## Compute the location and size of where this firmware image
@@ -40,7 +40,7 @@ end
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
@@ -67,7 +67,7 @@ else
     end
 end
 
-arch i386 end 
+arch i386 end
 
 ##
 ## Build the objects we have code for in this directory.
@@ -83,17 +83,17 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
 
 if USE_DCACHE_RAM
 
-	if CONFIG_USE_INIT	
+	if CONFIG_USE_INIT
 		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 		end
 	else
 		makerule ./cache_as_ram_auto.inc
-        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+			depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+			action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+			action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+			action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 		end
 	end
 
@@ -102,11 +102,11 @@ end
 if USE_FAILOVER_IMAGE
 else
     if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
-        end
-        ldscript /arch/i386/init/ldscript_apc.lb
+	makerule ./apc_auto.o
+		depends "$(MAINBOARD)/apc_auto.c option_table.h"
+		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+	end
+	ldscript /arch/i386/init/ldscript_apc.lb
     end
 end
 
@@ -129,13 +129,13 @@ end
 mainboardinit cpu/x86/32bit/entry32.inc
 
 if USE_DCACHE_RAM
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
+	if CONFIG_USE_INIT
+		ldscript /cpu/x86/32bit/entry32.lds
+	end
 
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
+	if CONFIG_USE_INIT
+		ldscript /cpu/amd/car/cache_as_ram.lds
+	end
 end
 
 
@@ -143,20 +143,20 @@ end
 ## Build our reset vector (This is where coreboot is entered)
 ##
 if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+    if USE_FAILOVER_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
     else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
     end
 else
-    if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+    if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
     else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
     end
 end
 
@@ -170,12 +170,12 @@ ldscript /southbridge/nvidia/mcp55/id.lds
 ## ROMSTRAP table for MCP55
 ##
 if HAVE_FAILOVER_BOOT
-    if USE_FAILOVER_IMAGE 
+    if USE_FAILOVER_IMAGE
 	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 	ldscript /southbridge/nvidia/mcp55/romstrap.lds
     end
 else
-    if USE_FALLBACK_IMAGE 
+    if USE_FALLBACK_IMAGE
 	mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 	ldscript /southbridge/nvidia/mcp55/romstrap.lds
     end
@@ -189,7 +189,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of coreboot startup 
+### This is the early phase of coreboot startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -220,159 +220,159 @@ if USE_DCACHE_RAM
 end
 
 ##
-## Include the secondary Configuration files 
+## Include the secondary Configuration files
 ##
 if CONFIG_CHIP_NAME
 	config chip.h
 end
 
 chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F
+			device apic 0 on end
+		end
+	end
 	device pci_domain 0 on
 		chip northbridge/amd/amdk8 #mc0
 			device pci 18.0 on end
-			device pci 18.0 on end 
-			device pci 18.0 on 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/mcp55 
+			device pci 18.0 on end
+			device pci 18.0 on
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/mcp55
 					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
+					device pci 1.0 on # LPC
 						chip superio/winbond/w83627hf
 							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
 							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
 							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
 							end
-                	        			device pnp 2e.3 on #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
+							device pnp 2e.3 on #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
 							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
 								irq 0x72 = 12
 							end
-                	        			device pnp 2e.6 off  # SFI 
-                	                 			io 0x62 = 0x100
+							device pnp 2e.6 off  # SFI
+								io 0x62 = 0x100
 							end
-                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
+							device pnp 2e.7 off #  GPIO_GAME_MIDI
 								io 0x60 = 0x220
 								io 0x62 = 0x300
 								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  WDTO_PLED
-                	        			device pnp 2e.9 off end #  GPIO_SUSLED
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
+							end
+							device pnp 2e.8 off end #  WDTO_PLED
+							device pnp 2e.9 off end #  GPIO_SUSLED
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+ 								io 0x60 = 0x290
 								irq 0x70 = 5
-                					end
+							end
 						end
 					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
 					end # SM
-                                        device pci 1.1 on # SM 1
+					device pci 1.1 on # SM 1
 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master MCP55 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
+#						chip drivers/generic/generic #PCIXA Slot1
+#							device i2c 50 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot1
+#							device i2c 51 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot2
+#							device i2c 52 on end
+#						end
+#						chip drivers/generic/generic #PCI Slot1
+#							device i2c 53 on end
+#						end
+#						chip drivers/generic/generic #Master MCP55 PCI-E
+#							device i2c 54 on end
+#						end
+#						chip drivers/generic/generic #Slave MCP55 PCI-E
+#							device i2c 55 on end
+#						end
+						chip drivers/generic/generic #MAC EEPROM
+							device i2c 51 on end
+						end
 
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-                			device pci 4.0 on end # IDE
-	                		device pci 5.0 on end # SATA 0
-	                		device pci 5.1 on end # SATA 1
-	                		device pci 5.2 on end # SATA 2
-                			device pci 6.0 on end # PCI
-        	        		device pci 6.1 off end # AZA
-	                		device pci 8.0 on end # NIC
-	                		device pci 9.0 on end # NIC
-        	       			device pci a.0 on end # PCI E 5
-        	       			device pci b.0 off end # PCI E 4
-                			device pci c.0 off end # PCI E 3
-                			device pci d.0 on end # PCI E 2
-                			device pci e.0 off end # PCI E 1
-        	       			device pci f.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
+					end # SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # IDE
+					device pci 5.0 on end # SATA 0
+					device pci 5.1 on end # SATA 1
+					device pci 5.2 on end # SATA 2
+					device pci 6.0 on end # PCI
+					device pci 6.1 off end # AZA
+					device pci 8.0 on end # NIC
+					device pci 9.0 on end # NIC
+					device pci a.0 on end # PCI E 5
+					device pci b.0 off end # PCI E 4
+					device pci c.0 off end # PCI E 3
+					device pci d.0 on end # PCI E 2
+					device pci e.0 off end # PCI E 1
+					device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
 				end
-			end #  device pci 18.0 
+			end #  device pci 18.0
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
-		
+
 	end # PCI domain
-	
-#       chip drivers/generic/debug 
-#               device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 on end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 on end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#               device pnp 0.7 off end # tsc
-#                device pnp 0.8 off  end # io
-#                device pnp 0.9 off end # io
-#       end  
+
+#       chip drivers/generic/debug
+#	       device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#	       device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#       end
 end #root_complex